From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Mon, 4 Mar 2019 17:22:22 +0000 (-0800)
Subject: Revert BRAM WRITE_MODE changes.
X-Git-Tag: yosys-0.9~266^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=228f132ec388fd8d0791ed3f0944b850de054370;p=yosys.git

Revert BRAM WRITE_MODE changes.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---

diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v
index 2a23b2553..7ea49158d 100644
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/brams_map.v
@@ -30,8 +30,8 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 		.RAM_MODE("SDP"),
 		.READ_WIDTH_A(72),
 		.WRITE_WIDTH_B(72),
-		.WRITE_MODE_A("WRITE_FIRST"),
-		.WRITE_MODE_B("WRITE_FIRST"),
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST"),
 		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 		`include "brams_init_36.vh"
@@ -95,8 +95,8 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 		.RAM_MODE("SDP"),
 		.READ_WIDTH_A(36),
 		.WRITE_WIDTH_B(36),
-		.WRITE_MODE_A("WRITE_FIRST"),
-		.WRITE_MODE_B("WRITE_FIRST"),
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST"),
 		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 		`include "brams_init_18.vh"
@@ -171,8 +171,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("WRITE_FIRST"),
-			.WRITE_MODE_B("WRITE_FIRST"),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_36.vh"
@@ -209,8 +209,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("WRITE_FIRST"),
-			.WRITE_MODE_B("WRITE_FIRST"),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_32.vh"
@@ -285,8 +285,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("WRITE_FIRST"),
-			.WRITE_MODE_B("WRITE_FIRST"),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_18.vh"
@@ -323,8 +323,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("WRITE_FIRST"),
-			.WRITE_MODE_B("WRITE_FIRST"),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_16.vh"