From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 30 Oct 2018 06:09:20 +0000 (+0000)
Subject: on scalar operation, sign-extend / zero-extend to full reg width
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2290b373d832c220d3381ff9ec1a0048513df160;p=riscv-isa-sim.git

on scalar operation, sign-extend / zero-extend to full reg width
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index d80fb08..684952f 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -84,15 +84,27 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
     }
     if (xlen != bitwidth)
     {
+        char *report = "";
         uint64_t data = _insn->p->get_state()->XPR[reg];
         uint64_t mask = ((1UL<<bitwidth)-1UL) << (shift*bitwidth);
         wval = (uint64_t)(wval << (shift*bitwidth)); // element within reg-block
         wval &= mask;
-        uint64_t ndata = data & (uint64_t)(~mask); // masks off the right bits
-        wval |= ndata;
-        fprintf(stderr, "writereg %ld bitwidth %d offs %d shift %d %lx " \
+        uint64_t ndata = data;
+        if (spec.isvec) {
+            ndata = data & (uint64_t)(~mask); // masks off right bits
+            wval |= ndata;
+        } else {
+            if (_insn->signextended) {
+                wval = sext_bwid(wval, bitwidth);
+                report = "s";
+            } else {
+                wval = zext_bwid(wval, bitwidth);
+                report = "z";
+            }
+        }
+        fprintf(stderr, "writereg %s %ld bitwidth %d offs %d shift %d %lx " \
                         " %lx %lx %lx\n",
-                        spec.reg, bitwidth, offs, shift, data,
+                        report, spec.reg, bitwidth, offs, shift, data,
                         ndata, mask, wval);
     }
     STATE.XPR.write(reg, wval);