From: Andrew Stubbs <ams@codesourcery.com>
Date: Wed, 5 Feb 2020 11:32:38 +0000 (+0000)
Subject: amdgcn: fix mode in vec_series
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2291d1fd85744f26bf4943187266d28c3b89d200;p=gcc.git

amdgcn: fix mode in vec_series

2020-02-21  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6e7de5fa729..543e95df1e0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2020-02-21  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
+
 2020-02-21  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index ecdd60b8190..edac362fd46 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -3156,7 +3156,7 @@
     rtx op1vec = gen_reg_rtx (V64DImode);
 
     emit_insn (gen_mulv64di3_zext_dup2 (tmp, v1, operands[2]));
-    emit_insn (gen_vec_duplicatev64si (op1vec, operands[1]));
+    emit_insn (gen_vec_duplicatev64di (op1vec, operands[1]));
     emit_insn (gen_addv64di3 (operands[0], tmp, op1vec));
     DONE;
   })