From: Eric Anholt <eric@anholt.net>
Date: Tue, 19 May 2020 23:26:37 +0000 (-0700)
Subject: freedreno/a5xx: Define the 2D blit UBWC pitch fields
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22979f90d9587e7f31c70d07b0b8517ff0bfcaa7;hp=6a154aea0d3375aa8469f28bb8a85e5ee79eef4a;p=mesa.git

freedreno/a5xx: Define the 2D blit UBWC pitch fields

Syncing up with my changes to envytools for decoding texturator output.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>
---

diff --git a/src/freedreno/registers/a5xx.xml b/src/freedreno/registers/a5xx.xml
index dc809cfb716..c5fdb662b8b 100644
--- a/src/freedreno/registers/a5xx.xml
+++ b/src/freedreno/registers/a5xx.xml
@@ -2773,8 +2773,10 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32?  not set
 	</reg32>
 	<reg32 offset="0x2140" name="RB_2D_SRC_FLAGS_LO"/>
 	<reg32 offset="0x2141" name="RB_2D_SRC_FLAGS_HI"/>
+        <reg32 offset="0x2142" name="RB_2D_SRC_FLAGS_PITCH" shr="6" type="uint"/>
 	<reg32 offset="0x2143" name="RB_2D_DST_FLAGS_LO"/>
 	<reg32 offset="0x2144" name="RB_2D_DST_FLAGS_HI"/>
+        <reg32 offset="0x2145" name="RB_2D_DST_FLAGS_PITCH" shr="6" type="uint"/>
 	<reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 -->
 	<!-- looks same as 0x2107: -->
 	<reg32 offset="0x2181" name="GRAS_2D_SRC_INFO">