From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 9 Apr 2015 11:37:07 +0000 (+0200)
Subject: Xilinx DRAMS: RAM64X1D, RAM128X1D
X-Git-Tag: yosys-0.6~339
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=229825e1b8936bd346829cf0ec9cf1fb3a67fc19;p=yosys.git

Xilinx DRAMS: RAM64X1D, RAM128X1D
---

diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt
index 84175b24c..5d2840ec0 100644
--- a/techlibs/xilinx/drams.txt
+++ b/techlibs/xilinx/drams.txt
@@ -1,7 +1,7 @@
 
-bram $__XILINX_RAM32X1D
+bram $__XILINX_RAM64X1D
   init 1
-  abits 5
+  abits 6
   dbits 1
   groups 2
   ports  1 1
@@ -12,6 +12,23 @@ bram $__XILINX_RAM32X1D
   clkpol 0 2
 endbram
 
-match $__XILINX_RAM32X1D
+bram $__XILINX_RAM128X1D
+  init 1
+  abits 7
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+match $__XILINX_RAM64X1D
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAM128X1D
 endmatch
 
diff --git a/techlibs/xilinx/drams_bb.v b/techlibs/xilinx/drams_bb.v
index f3169ab4f..11168fe13 100644
--- a/techlibs/xilinx/drams_bb.v
+++ b/techlibs/xilinx/drams_bb.v
@@ -1,11 +1,20 @@
 
-module RAM32X1D (
+module RAM64X1D (
 	output DPO, SPO,
-	input  A0, A1, A2, A3, A4, D,
-	input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
-	input  WCLK, WE
+	input  D, WCLK, WE,
+	input  A0, A1, A2, A3, A4, A5,
+	input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
-	parameter INIT = 32'h0;
+	parameter INIT = 64'h0;
+	parameter IS_WCLK_INVERTED = 1'b0;
+endmodule
+
+module RAM128X1D (
+	output       DPO, SPO,
+	input        D, WCLK, WE,
+	input  [6:0] A, DPRA
+);
+	parameter INIT = 128'h0;
 	parameter IS_WCLK_INVERTED = 1'b0;
 endmodule
 
diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v
index c0825150a..47476b592 100644
--- a/techlibs/xilinx/drams_map.v
+++ b/techlibs/xilinx/drams_map.v
@@ -1,17 +1,17 @@
 
-module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
-	parameter [31:0] INIT = 32'bx;
+module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0] INIT = 64'bx;
 	parameter CLKPOL2 = 1;
 	input CLK1;
 
-	input [4:0] A1ADDR;
+	input [5:0] A1ADDR;
 	output A1DATA;
 
-	input [4:0] B1ADDR;
+	input [5:0] B1ADDR;
 	input B1DATA;
 	input B1EN;
 
-	RAM32X1D #(
+	RAM64X1D #(
 		.INIT(INIT),
 		.IS_WCLK_INVERTED(!CLKPOL2)
 	) _TECHMAP_REPLACE_ (
@@ -20,6 +20,7 @@ module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 		.DPRA2(A1ADDR[2]),
 		.DPRA3(A1ADDR[3]),
 		.DPRA4(A1ADDR[4]),
+		.DPRA5(A1ADDR[5]),
 		.DPO(A1DATA),
 
 		.A0(B1ADDR[0]),
@@ -27,6 +28,33 @@ module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 		.A2(B1ADDR[2]),
 		.A3(B1ADDR[3]),
 		.A4(B1ADDR[4]),
+		.A5(B1ADDR[5]),
+		.D(B1DATA),
+		.WCLK(CLK1),
+		.WE(B1EN)
+	);
+endmodule
+
+module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [127:0] INIT = 128'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [6:0] A1ADDR;
+	output A1DATA;
+
+	input [6:0] B1ADDR;
+	input B1DATA;
+	input B1EN;
+
+	RAM128X1D #(
+		.INIT(INIT),
+		.IS_WCLK_INVERTED(!CLKPOL2)
+	) _TECHMAP_REPLACE_ (
+		.DPRA(A1ADDR),
+		.DPO(A1DATA),
+
+		.A(B1ADDR),
 		.D(B1DATA),
 		.WCLK(CLK1),
 		.WE(B1EN)