From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Wed, 4 Nov 2020 01:39:13 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1870
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22aaf6dd9473014f46b20b3d6411c24be78a331d;p=libreriscv.git

---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 80dca134a..203f81bc4 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -155,13 +155,23 @@ and therefore have no value are marked with 'NOT'
 
 ## Images of wires on FPGA and on STLINKV2
 
-[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="250x" ]]                                    
+Image of JTAG jumper wire connections on ULX3S FPGA side
 
-## Questions
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] 
 
-Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG?
+Image of JTAG jumper wire connections on STLINKV2 side
 
-Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
+(same orientation as JTAG pinout documentation)
+
+[[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]                                    
+
+Image of JTAG jumper wire connections on STLINKV2 side
+
+(opposite orientation as JTAG pinout documentation, 
+
+same orientation as 'ST' text on STLINKV2 device)
+
+[[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]                                    
 
 # STLinkV2 connector