From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 16 May 2023 04:34:20 +0000 (-0700)
Subject: auto-compute FPSCR exception summary bits
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22bc2b405cab799a7d69dfb119e9860a3bc09cfb;p=openpower-isa.git

auto-compute FPSCR exception summary bits
---

diff --git a/src/openpower/fpscr.py b/src/openpower/fpscr.py
index 1543948f..87640053 100644
--- a/src/openpower/fpscr.py
+++ b/src/openpower/fpscr.py
@@ -130,6 +130,7 @@ class FPSCR_FPRF(FieldSelectableInt):
 
 class FPSCRState(SelectableInt):
     def __init__(self, value=0):
+        self.__do_update_computed_bits = False
         SelectableInt.__init__(self, value, 64)
         self.fsi = {}
         offs = 0
@@ -163,6 +164,39 @@ class FPSCRState(SelectableInt):
                 fs = tuple(offs)
             v = FieldSelectableInt(self, fs)
             self.fsi[field] = v
+        self.__update_computed_bits()
+
+    @property
+    def value(self):
+        return self.__value
+
+    @value.setter
+    def value(self, value):
+        self.__value = value
+        if self.__do_update_computed_bits:
+            self.__update_computed_bits()
+
+    def __update_computed_bits(self):
+        self.__do_update_computed_bits = False
+        try:
+            # update summary bits -- FX is manually handled by pseudo-code,
+            # so we don't update it here
+            self.VX = (self.VXSNAN |
+                       self.VXISI |
+                       self.VXIDI |
+                       self.VXZDZ |
+                       self.VXIMZ |
+                       self.VXVC |
+                       self.VXSOFT |
+                       self.VXSQRT |
+                       self.VXCVI)
+            self.FEX = ((self.VX & self.VE) |
+                        (self.OX & self.OE) |
+                        (self.UX & self.UE) |
+                        (self.ZX & self.ZE) |
+                        (self.XX & self.XE))
+        finally:
+            self.__do_update_computed_bits = True
 
     @property
     def DRN(self):
diff --git a/src/openpower/test_fpscr.py b/src/openpower/test_fpscr.py
index 6652b8f1..00ea2f8f 100644
--- a/src/openpower/test_fpscr.py
+++ b/src/openpower/test_fpscr.py
@@ -12,9 +12,12 @@ class TestFPSCR(unittest.TestCase):
         expected = 0x3
         self.assertEqual(FPSCR, expected)
         self.assertEqual(FPSCR.VXCVI, 0)
+        self.assertEqual(FPSCR.VX, 0)
         FPSCR.VXCVI = 1
         self.assertEqual(FPSCR.VXCVI, 1)
+        self.assertEqual(FPSCR.VX, 1)
         expected |= 1 << (64 - 55 - 1)
+        expected |= 1 << (64 - 34 - 1)
         self.assertEqual(FPSCR, expected)
         self.assertEqual(FPSCR.FX, 0)
         FPSCR.FX = 1
@@ -35,6 +38,15 @@ class TestFPSCR(unittest.TestCase):
         self.assertEqual(FPSCR, expected)
         self.assertEqual(FPSCR.FPRF, 0b10010)
         self.assertEqual(FPSCR.FPCC, 0b0010)
+        self.assertEqual(FPSCR.VE, 0)
+        self.assertEqual(FPSCR.VX, 1)
+        self.assertEqual(FPSCR.FEX, 0)
+        FPSCR.VE = 1
+        self.assertEqual(FPSCR.VE, 1)
+        self.assertEqual(FPSCR.FEX, 1)
+        expected |= 1 << (64 - 56 - 1)
+        expected |= 1 << (64 - 33 - 1)
+        self.assertEqual(FPSCR, expected)
 
 
 if __name__ == "__main__":