From: Michael Collison Date: Fri, 27 Oct 2017 06:05:58 +0000 (+0000) Subject: aarch64.md (_trunc>2): New pattern. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22be0d084c010c8c798f397d628759d259b15a92;p=gcc.git aarch64.md (_trunc>2): New pattern. 2017-10-26 Michael Collison * config/aarch64/aarch64.md(_trunc>2): New pattern. (_trunchf2: New pattern. (_trunc2: New pattern. * config/aarch64/iterators.md (wv): New mode attribute. (vf, VF): New mode attributes. (vgp, VGP): New mode attributes. (s): Update attribute with SImode and DImode prefixes. * testsuite/gcc.target/aarch64/fix_trunc1.c: New testcase. * testsuite/gcc.target/aarch64/vect-vcvt.c: Fix scan-assembler directives to allow float or integer destination registers for fcvtz[su]. From-SVN: r254133 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 558ec9bf7f2..e9418ee98fe 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2017-10-26 Michael Collison + + * config/aarch64/aarch64.md(_trunc>2): + New pattern. + (_trunchf2: New pattern. + (_trunc2: New pattern. + * config/aarch64/iterators.md (wv): New mode attribute. + (vf, VF): New mode attributes. + (vgp, VGP): New mode attributes. + (s): Update attribute with SImode and DImode prefixes. + 2017-10-26 Sandra Loosemore * config/nios2/constraints.md ("S"): Match r0rel_constant_p too. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index eee836be055..bbd5174df75 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4849,11 +4849,37 @@ [(set_attr "type" "f_cvt")] ) -(define_insn "_trunc2" +;; Convert SF -> SI or DF -> DI while preferring w = w register constraints +;; and making r = w more expensive + +(define_insn "_trunc2" + [(set (match_operand:GPI 0 "register_operand" "=?r,w") + (FIXUORS:GPI (match_operand: 1 "register_operand" "w,w")))] + "TARGET_FLOAT" + "@ + fcvtz\t%0, %1 + fcvtz\t%0, %1" + [(set_attr "type" "f_cvtf2i,neon_fp_to_int_s")] +) + +;; Convert HF -> SI or DI + +(define_insn "_trunchf2" + [(set (match_operand:GPI 0 "register_operand" "=r") + (FIXUORS:GPI (match_operand:HF 1 "register_operand" "w")))] + "TARGET_FP_F16INST" + "fcvtz\t%0, %h1" + [(set_attr "type" "f_cvtf2i")] +) + +;; Convert DF -> SI or SF -> DI which can only be accomplished with +;; input in a fp register and output in a integer register + +(define_insn "_trunc2" [(set (match_operand:GPI 0 "register_operand" "=r") - (FIXUORS:GPI (match_operand:GPF_F16 1 "register_operand" "w")))] + (FIXUORS:GPI (match_operand: 1 "register_operand" "w")))] "TARGET_FLOAT" - "fcvtz\t%0, %1" + "fcvtz\t%0, %1" [(set_attr "type" "f_cvtf2i")] ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 48cedbe84a6..68da3165320 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -398,6 +398,9 @@ (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) +;; For width of fp registers in fcvt instruction +(define_mode_attr fpw [(DI "s") (SI "d")]) + (define_mode_attr short_mask [(HI "65535") (QI "255")]) ;; For constraints used in scalar immediate vector moves @@ -406,6 +409,10 @@ ;; For doubling width of an integer mode (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) +(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")]) + +(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")]) + ;; For scalar usage of vector/FP registers (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") (HF "h") (SF "s") (DF "d") @@ -438,8 +445,8 @@ (define_mode_attr rtn [(DI "d") (SI "")]) (define_mode_attr vas [(DI "") (SI ".2s")]) -;; Map a floating point mode to the appropriate register name prefix -(define_mode_attr s [(HF "h") (SF "s") (DF "d")]) +;; Map a floating point or integer mode to the appropriate register name prefix +(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) ;; Give the length suffix letter for a sign- or zero-extension. (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2f840a96f75..a545b7fd7ea 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-10-26 Michael Collison + + * gcc.target/aarch64/fix_trunc1.c: New testcase. + * gcc.target/aarch64/vect-vcvt.c: Fix scan-assembler + directives to allow float or integer destination registers for + fcvtz[su]. + 2017-10-26 Sandra Loosemore * gcc.target/nios2/gpopt-r0rel-sec.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/fix_trunc1.c b/gcc/testsuite/gcc.target/aarch64/fix_trunc1.c new file mode 100644 index 00000000000..0441458f635 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fix_trunc1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +float +f1 (float x) +{ + int y = x; + + return (float) y; +} + +double +f2 (double x) +{ + long y = x; + + return (double) y; +} + +/* { dg-final { scan-assembler "fcvtzs\\ts\[0-9\]+, s\[0-9\]+" } } */ +/* { dg-final { scan-assembler "scvtf\\ts\[0-9\]+, s\[0-9\]+" } } */ +/* { dg-final { scan-assembler "fcvtzs\\td\[0-9\]+, d\[0-9\]+" } } */ +/* { dg-final { scan-assembler "scvtf\\td\[0-9\]+, d\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c b/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c index a1422d7090b..436399c6195 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c @@ -56,13 +56,13 @@ TEST (SUFFIX, q, 32, 4, u,u,s) \ TEST (SUFFIX, q, 64, 2, u,u,d) \ BUILD_VARIANTS ( ) -/* { dg-final { scan-assembler "fcvtzs\\tw\[0-9\]+, s\[0-9\]+" } } */ -/* { dg-final { scan-assembler "fcvtzs\\tx\[0-9\]+, d\[0-9\]+" } } */ +/* { dg-final { scan-assembler "fcvtzs\\t(w|s)\[0-9\]+, s\[0-9\]+" } } */ +/* { dg-final { scan-assembler "fcvtzs\\t(x|d)\[0-9\]+, d\[0-9\]+" } } */ /* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ /* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ /* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ -/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */ -/* { dg-final { scan-assembler "fcvtzu\\tx\[0-9\]+, d\[0-9\]+" } } */ +/* { dg-final { scan-assembler "fcvtzu\\t(w|s)\[0-9\]+, s\[0-9\]+" } } */ +/* { dg-final { scan-assembler "fcvtzu\\t(x|d)\[0-9\]+, d\[0-9\]+" } } */ /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */