From: Nanley Chery <nanley.g.chery@intel.com>
Date: Wed, 27 Mar 2019 21:40:58 +0000 (-0700)
Subject: isl/drm: Map HiZ and CCS tilings to Y
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22be1447bb46b4dc63fbc2cfc696c01a0f90ab0e;p=mesa.git

isl/drm: Map HiZ and CCS tilings to Y

In the function which translates ISL tilings to i915 tilings, map ISL's
HiZ and CCS tilings to Y instead of NONE (linear). The HW docs describe
HiZ and pre-Gen12 CCS surfaces as being Y-tiled in memory.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
---

diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index e7abe747785..196ecf7f88c 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -41,13 +41,13 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
       return I915_TILING_X;
 
    case ISL_TILING_Y0:
+   case ISL_TILING_HIZ:
+   case ISL_TILING_CCS:
       return I915_TILING_Y;
 
    case ISL_TILING_W:
    case ISL_TILING_Yf:
    case ISL_TILING_Ys:
-   case ISL_TILING_HIZ:
-   case ISL_TILING_CCS:
       return I915_TILING_NONE;
    }