From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 12 May 2021 12:04:37 +0000 (+0100)
Subject: no need for sel0
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22c4700827c9ac1788c919b5a85d860412d77ff3;p=soc.git

no need for sel0
---

diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py
index 4f7e4705..71dc89ca 100644
--- a/src/soc/experiment/cache_ram.py
+++ b/src/soc/experiment/cache_ram.py
@@ -31,10 +31,8 @@ class CacheRam(Elaboratable):
      
         rd_data0 = Signal(WIDTH)
      
-        sel0 = Signal(WIDTH//8) # defaults to zero
-
         with m.If(TRACE):
-            with m.If(self.wr_sel != sel0):
+            with m.If(self.wr_sel.bool()):
                 sync += Display( "write a: %x sel: %x dat: %x",
                                 self.wr_addr, self.wr_sel, self.wr_data)
         for i in range(WIDTH//8):