From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 24 Feb 2016 08:16:43 +0000 (+0100)
Subject: Fixed BLIF parser for empty port assignments
X-Git-Tag: yosys-0.6~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22c549ab37233eedf783f130a3dbd91749d98222;p=yosys.git

Fixed BLIF parser for empty port assignments
---

diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 202958496..ee0e771e9 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -267,10 +267,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 
 				while ((p = strtok(NULL, " \t\r\n")) != NULL) {
 					char *q = strchr(p, '=');
-					if (q == NULL || !q[0] || !q[1])
+					if (q == NULL || !q[0])
 						goto error;
 					*(q++) = 0;
-					cell->setPort(RTLIL::escape_id(p), blif_wire(q));
+					cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
 				}
 
 				obj_attributes = &cell->attributes;