From: Luke Kenneth Casson Leighton Date: Sun, 31 Jan 2021 16:01:16 +0000 (+0000) Subject: remove sv_rm from PowerDecoder register decoders X-Git-Tag: convert-csv-opcode-to-binary~278 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22f8aa5cda05f3c32d88cb247df8c924767481a4;p=soc.git remove sv_rm from PowerDecoder register decoders --- diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index dfd69339..bec44541 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -1,3 +1,7 @@ +# SPDX-License-Identifier: LGPLv3+ +# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton +# Copyright (C) 2020 Michael Nolan +# Funded by NLnet http://nlnet.nl """core of the python-based POWER9 simulator this is part of a cycle-accurate POWER9 simulator. its primary purpose is diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index b8b35285..72b0e246 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -421,7 +421,6 @@ class DecodeC(Elaboratable): def __init__(self, dec): self.dec = dec - self.sv_rm = SVP64Rec() # SVP64 RM field self.sel_in = Signal(In3Sel, reset_less=True) self.insn_in = Signal(32, reset_less=True) self.reg_out = Data(5, "reg_c") @@ -453,7 +452,6 @@ class DecodeOut(Elaboratable): def __init__(self, dec): self.dec = dec - self.sv_rm = SVP64Rec() # SVP64 RM field self.sel_in = Signal(OutSel, reset_less=True) self.insn_in = Signal(32, reset_less=True) self.reg_out = Data(5, "reg_o") @@ -518,7 +516,6 @@ class DecodeOut2(Elaboratable): def __init__(self, dec): self.dec = dec - self.sv_rm = SVP64Rec() # SVP64 RM field self.sel_in = Signal(OutSel, reset_less=True) self.lk = Signal(reset_less=True) self.insn_in = Signal(32, reset_less=True) @@ -646,7 +643,6 @@ class DecodeCRIn(Elaboratable): def __init__(self, dec): self.dec = dec - self.sv_rm = SVP64Rec() # SVP64 RM field self.sel_in = Signal(CRInSel, reset_less=True) self.insn_in = Signal(32, reset_less=True) self.cr_bitfield = Data(3, "cr_bitfield") @@ -1055,11 +1051,6 @@ class PowerDecode2(PowerDecodeSubset): dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]: comb += i.eq(self.dec.opcode_in) - # ... and svp64 rm - for i in [dec_a.insn_in, dec_b.insn_in, - dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]: - comb += i.eq(self.sv_rm) - # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv # which in turn were auto-generated by sv_analysis.py