From: Florent Kermarrec Date: Mon, 24 Sep 2018 08:58:10 +0000 (+0200) Subject: boards/targets: uniformize things between targets X-Git-Tag: 24jan2021_ls180~1590 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=22febe9582c903078c0c1d0fd25f277d1632dc41;p=litex.git boards/targets: uniformize things between targets --- diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 7552d9a6..021d2678 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -99,7 +99,8 @@ class BaseSoC(SoCSDRAM): csr_map.update(SoCSDRAM.csr_map) def __init__(self, **kwargs): platform = arty.Platform() - SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, + sys_clk_freq = int(100e6) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) @@ -107,8 +108,8 @@ class BaseSoC(SoCSDRAM): self.submodules.crg = _CRG(platform) # sdram - self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram")) - sdram_module = MT41K128M16(self.clk_freq, "1:4") + self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) + sdram_module = MT41K128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 813241a9..e46c5757 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -13,43 +13,44 @@ from litedram.modules import IS42S16160 from litedram.phy import GENSDRPHY -class _PLL(Module): +class _ALTPLL(Module): def __init__(self, period_in, name, phase_shift, operation_mode): self.clk_in = Signal() self.clk_out = Signal() - self.specials += Instance("ALTPLL", - p_bandwidth_type = "AUTO", - p_clk0_divide_by = 1, - p_clk0_duty_cycle = 50, - p_clk0_multiply_by = 2, - p_clk0_phase_shift = "{}".format(str(phase_shift)), - p_compensate_clock = "CLK0", - p_inclk0_input_frequency = int(period_in*1000), - p_intended_device_family = "Cyclone IV E", - p_lpm_hint = "CBX_MODULE_PREFIX={}_pll".format(name), - p_lpm_type = "altpll", - p_operation_mode = operation_mode, - i_inclk=self.clk_in, - o_clk=self.clk_out, - i_areset=0, - i_clkena=0x3f, - i_clkswitch=0, - i_configupdate=0, - i_extclkena=0xf, - i_fbin=1, - i_pfdena=1, - i_phasecounterselect=0xf, - i_phasestep=1, - i_phaseupdown=1, - i_pllena=1, - i_scanaclr=0, - i_scanclk=0, - i_scanclkena=1, - i_scandata=0, - i_scanread=0, - i_scanwrite=0 - ) + self.specials += \ + Instance("ALTPLL", + p_bandwidth_type = "AUTO", + p_clk0_divide_by = 1, + p_clk0_duty_cycle = 50, + p_clk0_multiply_by = 2, + p_clk0_phase_shift = "{}".format(str(phase_shift)), + p_compensate_clock = "CLK0", + p_inclk0_input_frequency = int(period_in*1000), + p_intended_device_family = "Cyclone IV E", + p_lpm_hint = "CBX_MODULE_PREFIX={}_pll".format(name), + p_lpm_type = "altpll", + p_operation_mode = operation_mode, + i_inclk=self.clk_in, + o_clk=self.clk_out, + i_areset=0, + i_clkena=0x3f, + i_clkswitch=0, + i_configupdate=0, + i_extclkena=0xf, + i_fbin=1, + i_pfdena=1, + i_phasecounterselect=0xf, + i_phasestep=1, + i_phaseupdown=1, + i_pllena=1, + i_scanaclr=0, + i_scanclk=0, + i_scanclkena=1, + i_scandata=0, + i_scanread=0, + i_scanwrite=0 + ) class _CRG(Module): @@ -60,14 +61,14 @@ class _CRG(Module): clk50 = platform.request("clk50") - sys_pll = _PLL(20, "sys", 0, "NORMAL") + sys_pll = _ALTPLL(20, "sys", 0, "NORMAL") self.submodules += sys_pll self.comb += [ sys_pll.clk_in.eq(clk50), self.cd_sys.clk.eq(sys_pll.clk_out) ] - sdram_pll = _PLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER") + sdram_pll = _ALTPLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER") self.submodules += sdram_pll self.comb += [ sdram_pll.clk_in.eq(clk50), @@ -89,15 +90,15 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): def __init__(self, **kwargs): platform = de0nano.Platform() - SoCSDRAM.__init__(self, platform, - clk_freq=100*1000000, + sys_clk_freq = int(100e6) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) sdram_module = IS42S16160(self.clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 8f2cb9ac..68431922 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -81,7 +81,8 @@ class BaseSoC(SoCSDRAM): csr_map.update(SoCSDRAM.csr_map) def __init__(self, **kwargs): platform = genesys2.Platform() - SoCSDRAM.__init__(self, platform, clk_freq=125*1000000, + sys_clk_freq = int(125e6) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) @@ -89,7 +90,7 @@ class BaseSoC(SoCSDRAM): self.submodules.crg = _CRG(platform) # sdram - self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram")) + self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) sdram_module = MT41J256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index cdc9c8ab..bbe42d8d 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -81,7 +81,8 @@ class BaseSoC(SoCSDRAM): csr_map.update(SoCSDRAM.csr_map) def __init__(self, **kwargs): platform = kc705.Platform() - SoCSDRAM.__init__(self, platform, clk_freq=125*1000000, + sys_clk_freq = int(125e6) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) @@ -89,8 +90,8 @@ class BaseSoC(SoCSDRAM): self.submodules.crg = _CRG(platform) # sdram - self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram")) - sdram_module = MT8JTF12864(self.clk_freq, "1:4") + self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) + sdram_module = MT8JTF12864(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 6cff5bee..44744073 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -68,17 +68,17 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): def __init__(self, **kwargs): - clk_freq = 80*1000000 platform = minispartan6.Platform() - SoCSDRAM.__init__(self, platform, clk_freq, + sys_clk_freq = int(80e6) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) - self.submodules.crg = _CRG(platform, clk_freq) + self.submodules.crg = _CRG(platform, sys_clk_freq) if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - sdram_module = AS4C16M16(clk_freq, "1:1") + sdram_module = AS4C16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index fb1e2e2d..f65c5d7f 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -95,7 +95,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq) - sdram_module = MT47H64M16(self.clk_freq, "1:2") + sdram_module = MT47H64M16(sys_clk_freq, "1:2") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index c3fc82f7..8e9acaf4 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -88,7 +88,8 @@ class BaseSoC(SoCSDRAM): csr_map.update(SoCSDRAM.csr_map) def __init__(self, **kwargs): platform = nexys_video.Platform() - SoCSDRAM.__init__(self, platform, clk_freq=100*1000000, + sys_clk_freq = int(100e6) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) @@ -96,8 +97,8 @@ class BaseSoC(SoCSDRAM): self.submodules.crg = _CRG(platform) # sdram - self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram")) - sdram_module = MT41K256M16(self.clk_freq, "1:4") + self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) + sdram_module = MT41K256M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index 9d8e1cce..4673569f 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -63,8 +63,8 @@ class SimSoC(SoCSDRAM): with_analyzer=False, **kwargs): platform = sim.Platform() - SoCSDRAM.__init__(self, platform, - clk_freq=int(1e9/platform.default_clk_period), + sys_clk_freq = int(1e9/platform.default_clk_period) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, @@ -78,7 +78,7 @@ class SimSoC(SoCSDRAM): # sdram if with_sdram: - sdram_module = IS42S16160(self.clk_freq, "1:1") + sdram_module = IS42S16160(sys_clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, @@ -122,7 +122,7 @@ class SimSoC(SoCSDRAM): self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME # eth core etherbonecore = LiteEthUDPIPCore(self.etherbonephy, - etherbone_mac_address, convert_ip(etherbone_ip_address), self.clk_freq) + etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq) if with_ethernet: etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore) self.submodules.etherbonecore = etherbonecore @@ -134,8 +134,8 @@ class SimSoC(SoCSDRAM): if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe - self.cpu_or_bridge.ibus, - self.cpu_or_bridge.dbus + self.cpu.ibus, + self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 03d9cc6f..ee1a4a7c 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -14,8 +14,8 @@ from liteeth.core.mac import LiteEthMAC class BaseSoC(SoCCore): def __init__(self, platform, **kwargs): - SoCCore.__init__(self, platform, - clk_freq=int((1/(platform.default_clk_period))*1000000000), + sys_clk_freq = int(1e9/platform.default_clk_period) + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, integrated_main_ram_size=16*1024, **kwargs)