From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 15 Oct 2014 10:13:22 +0000 (+0200)
Subject: uart2wishbone: always use payload.d and not .d
X-Git-Tag: 24jan2021_ls180~2575^2~54
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2319ee0ab7e62b5510387ccd4c8adb09fc42d8c9;p=litex.git

uart2wishbone: always use payload.d and not .d
---

diff --git a/miscope/uart2wishbone.py b/miscope/uart2wishbone.py
index f75a8574..f2c579be 100644
--- a/miscope/uart2wishbone.py
+++ b/miscope/uart2wishbone.py
@@ -103,7 +103,7 @@ class UART2Wishbone(Module, AutoCSR):
 			burst_cnt.clr.eq(1)
 			)
 		)
-		self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.source.stb, cmd.eq(uart.rx.source.d))
+		self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.source.stb, cmd.eq(uart.rx.source.payload.d))
 
 		####
 		burst_length = Signal(8)
@@ -115,7 +115,7 @@ class UART2Wishbone(Module, AutoCSR):
 			)
 		)
 		self.sync += \
-			If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.source.stb, burst_length.eq(uart.rx.source.d))
+			If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.source.stb, burst_length.eq(uart.rx.source.payload.d))
 
 		####
 		address = Signal(32)
@@ -132,7 +132,7 @@ class UART2Wishbone(Module, AutoCSR):
 		)
 		self.sync += \
 			If(fsm.ongoing("RECEIVE_ADDRESS") & uart.rx.source.stb,
-					address.eq(Cat(uart.rx.source.d, address[0:24]))
+					address.eq(Cat(uart.rx.source.payload.d, address[0:24]))
 			)
 
 		###
@@ -195,7 +195,7 @@ class UART2Wishbone(Module, AutoCSR):
 		###
 		self.sync += \
 			If(fsm.ongoing("RECEIVE_DATA") & uart.rx.source.stb,
-				data.eq(Cat(uart.rx.source.d, data[0:24]))
+				data.eq(Cat(uart.rx.source.payload.d, data[0:24]))
 			).Elif(fsm.ongoing("READ_DATA") & self.wishbone.stb & self.wishbone.ack,
 				data.eq(self.wishbone.dat_r)
 			)