From: Sam Tebbs Date: Thu, 13 Sep 2018 09:46:55 +0000 (+0000) Subject: [Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=231c52ae41a335649013f9fbfabca337d1ea98fa;p=gcc.git [Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks 2018-09-13 Sam Tebbs PR target/85628 * config/aarch64/aarch64.md (*aarch64_bfxil): Define. * config/aarch64/constraints.md (Ulc): Define. * config/aarch64/aarch64-protos.h (aarch64_high_bits_all_ones_p): Define. * config/aarch64/aarch64.c (aarch64_high_bits_all_ones_p): New function. * gcc.target/aarch64/combine_bfxil.c: New file. * gcc.target/aarch64/combine_bfxil_2.c: New file. From-SVN: r264264 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d9a383f90a8..99b894bb367 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2018-09-13 Sam Tebbs + + PR target/85628 + * config/aarch64/aarch64.md (*aarch64_bfxil): + Define. + * config/aarch64/constraints.md (Ulc): Define. + * config/aarch64/aarch64-protos.h (aarch64_high_bits_all_ones_p): + Define. + * config/aarch64/aarch64.c (aarch64_high_bits_all_ones_p): + New function. + 2018-09-13 Vlad Lazar * config/aarch64/aarch64.h (TARGET_COMPUTE_FRAME_LAYOUT): Define. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index aae1db45ed6..b26e46f81a4 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -624,4 +624,6 @@ rtl_opt_pass *make_pass_tag_collision_avoidance (gcc::context *); poly_uint64 aarch64_regmode_natural_size (machine_mode); +bool aarch64_high_bits_all_ones_p (HOST_WIDE_INT); + #endif /* GCC_AARCH64_PROTOS_H */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 1240bed5497..8cc738c11f0 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1432,6 +1432,13 @@ aarch64_hard_regno_caller_save_mode (unsigned regno, unsigned, return SImode; } +/* Return true if I's bits are consecutive ones from the MSB. */ +bool +aarch64_high_bits_all_ones_p (HOST_WIDE_INT i) +{ + return exact_log2 (-i) != HOST_WIDE_INT_M1; +} + /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so that strcpy from constants will be faster. */ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 955769a64d2..88f66104db3 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5336,6 +5336,31 @@ [(set_attr "type" "rev")] ) +(define_insn "*aarch64_bfxil" + [(set (match_operand:GPI 0 "register_operand" "=r,r") + (ior:GPI (and:GPI (match_operand:GPI 1 "register_operand" "r,0") + (match_operand:GPI 3 "const_int_operand" "n, Ulc")) + (and:GPI (match_operand:GPI 2 "register_operand" "0,r") + (match_operand:GPI 4 "const_int_operand" "Ulc, n"))))] + "(INTVAL (operands[3]) == ~INTVAL (operands[4])) + && (aarch64_high_bits_all_ones_p (INTVAL (operands[3])) + || aarch64_high_bits_all_ones_p (INTVAL (operands[4])))" + { + switch (which_alternative) + { + case 0: + operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[3]))); + return "bfxil\\t%0, %1, 0, %3"; + case 1: + operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[4]))); + return "bfxil\\t%0, %2, 0, %3"; + default: + gcc_unreachable (); + } + } + [(set_attr "type" "bfm")] +) + ;; There are no canonicalisation rules for the position of the lshiftrt, ashift ;; operations within an IOR/AND RTX, therefore we have two patterns matching ;; each valid permutation. diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 72cacdabdac..31fc3eafd8b 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -172,6 +172,13 @@ A constraint that matches the immediate constant -1." (match_test "op == constm1_rtx")) +(define_constraint "Ulc" + "@internal + A constraint that matches a constant integer whose bits are consecutive ones + from the MSB." + (and (match_code "const_int") + (match_test "aarch64_high_bits_all_ones_p (ival)"))) + (define_constraint "Usv" "@internal A constraint that matches a VG-based constant that can be loaded by diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1e5f8827ac9..08915bbd5a3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2018-09-13 Sam Tebbs + + PR target/85628 + * gcc.target/aarch64/combine_bfxil.c: New file. + * gcc.target/aarch64/combine_bfxil_2.c: New file. + 2018-09-13 Jakub Jelinek Kyrylo Tkachov diff --git a/gcc/testsuite/gcc.target/aarch64/combine_bfxil.c b/gcc/testsuite/gcc.target/aarch64/combine_bfxil.c new file mode 100644 index 00000000000..adb0582ed9d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/combine_bfxil.c @@ -0,0 +1,98 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); + +unsigned long long +combine_balanced (unsigned long long a, unsigned long long b) +{ + return (a & 0xffffffff00000000ll) | (b & 0x00000000ffffffffll); +} + +unsigned long long +combine_minimal (unsigned long long a, unsigned long long b) +{ + return (a & 0xfffffffffffffffe) | (b & 0x0000000000000001); +} + +unsigned long long +combine_unbalanced (unsigned long long a, unsigned long long b) +{ + return (a & 0xffffffffff000000ll) | (b & 0x0000000000ffffffll); +} + +unsigned int +combine_balanced_int (unsigned int a, unsigned int b) +{ + return (a & 0xffff0000ll) | (b & 0x0000ffffll); +} + +unsigned int +combine_unbalanced_int (unsigned int a, unsigned int b) +{ + return (a & 0xffffff00ll) | (b & 0x000000ffll); +} + +__attribute__ ((noinline)) void +foo (unsigned long long a, unsigned long long b, unsigned long long *c, + unsigned long long *d) +{ + *c = combine_minimal (a, b); + *d = combine_minimal (b, a); +} + +__attribute__ ((noinline)) void +foo2 (unsigned long long a, unsigned long long b, unsigned long long *c, + unsigned long long *d) +{ + *c = combine_balanced (a, b); + *d = combine_balanced (b, a); +} + +__attribute__ ((noinline)) void +foo3 (unsigned long long a, unsigned long long b, unsigned long long *c, + unsigned long long *d) +{ + *c = combine_unbalanced (a, b); + *d = combine_unbalanced (b, a); +} + +void +foo4 (unsigned int a, unsigned int b, unsigned int *c, unsigned int *d) +{ + *c = combine_balanced_int (a, b); + *d = combine_balanced_int (b, a); +} + +void +foo5 (unsigned int a, unsigned int b, unsigned int *c, unsigned int *d) +{ + *c = combine_unbalanced_int (a, b); + *d = combine_unbalanced_int (b, a); +} + +int +main (void) +{ + unsigned long long a = 0x0123456789ABCDEF, b = 0xFEDCBA9876543210, c, d; + foo3 (a, b, &c, &d); + if (c != 0x0123456789543210) abort (); + if (d != 0xfedcba9876abcdef) abort (); + foo2 (a, b, &c, &d); + if (c != 0x0123456776543210) abort (); + if (d != 0xfedcba9889abcdef) abort (); + foo (a, b, &c, &d); + if (c != 0x0123456789abcdee) abort (); + if (d != 0xfedcba9876543211) abort (); + + unsigned int a2 = 0x01234567, b2 = 0xFEDCBA98, c2, d2; + foo4 (a2, b2, &c2, &d2); + if (c2 != 0x0123ba98) abort (); + if (d2 != 0xfedc4567) abort (); + foo5 (a2, b2, &c2, &d2); + if (c2 != 0x01234598) abort (); + if (d2 != 0xfedcba67) abort (); + return 0; +} + +/* { dg-final { scan-assembler-times "bfxil\\t" 10 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/combine_bfxil_2.c b/gcc/testsuite/gcc.target/aarch64/combine_bfxil_2.c new file mode 100644 index 00000000000..0fc140443bc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/combine_bfxil_2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long long +combine_non_consecutive (unsigned long long a, unsigned long long b) +{ + return (a & 0xfffffff200f00000ll) | (b & 0x00001000ffffffffll); +} + +void +foo4 (unsigned long long a, unsigned long long b, unsigned long long *c, + unsigned long long *d) { + /* { dg-final { scan-assembler-not "bfxil\\t" } } */ + *c = combine_non_consecutive (a, b); + *d = combine_non_consecutive (b, a); +}