From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 18:02:17 +0000 (-0700)
Subject: Forgot to set ud_variable.minlen
X-Git-Tag: working-ls180~1085^2~65
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=231ddbf95cb2541eb73622e7dcb2744b2308f584;p=yosys.git

Forgot to set ud_variable.minlen
---

diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index 36833839b..d1dbd77ae 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -204,6 +204,7 @@ struct XilinxSrlPass : public Pass {
 		for (auto module : design->selected_modules()) {
 			auto pm = xilinx_srl_pm(module, module->selected_cells());
 			pm.ud_fixed.minlen = minlen;
+			pm.ud_variable.minlen = minlen;
 
 			if (fixed) {
 				// TODO: How to get these automatically?