From: whitequark Date: Sun, 14 Jun 2020 09:38:32 +0000 (+0000) Subject: back.verilog: refactor Yosys script generation. NFCI. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=232336cfd2a49b18bc6366e1eecc527dccc7a7ce;p=nmigen.git back.verilog: refactor Yosys script generation. NFCI. In commit 5f30bcbb, back.cxxsim gained a nicer way to generate a script; this commit brings it to back.verilog too. --- diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py index cb684ab..1d2cb4a 100644 --- a/nmigen/back/verilog.py +++ b/nmigen/back/verilog.py @@ -10,39 +10,36 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog yosys = find_yosys(lambda ver: ver >= (0, 9)) yosys_version = yosys.version() - attr_map = [] + script = [] + script.append("read_ilang <= (0, 9, 231): + # Yosys 0.9 release has buggy proc_prune. + script.append("delete w:$verilog_initial_trigger") + script.append("proc_prune") + script.append("proc_init") + script.append("proc_arst") + script.append("proc_dff") + script.append("proc_clean") + script.append("memory_collect") + if strip_internal_attrs: + attr_map = [] attr_map.append("-remove generator") attr_map.append("-remove top") attr_map.append("-remove src") attr_map.append("-remove nmigen.hierarchy") attr_map.append("-remove nmigen.decoding") + script.append("attrmap {}".format(" ".join(attr_map))) + script.append("attrmap -modattr {}".format(" ".join(attr_map))) - return yosys.run(["-q", "-"], """ -# Convert nMigen's RTLIL to readable Verilog. -read_ilang <