From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Jul 2019 22:37:35 +0000 (-0700)
Subject: mul2dsp to create cells that can be interchanged with $mul
X-Git-Tag: working-ls180~1039^2~333
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2339b7fc3732996a217f635d95f1f7400cf43d48;p=yosys.git

mul2dsp to create cells that can be interchanged with $mul
---

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index ee53701ee..391b395ff 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -214,7 +214,13 @@ module \$__mul_gen (A, B, Y);
 			else
 				wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
 
-			`DSP_NAME _TECHMAP_REPLACE_ (
+			`DSP_NAME #(
+				.A_SIGNED(A_SIGNED),
+				.B_SIGNED(B_SIGNED),
+				.A_WIDTH(`DSP_A_MAXWIDTH),
+				.B_WIDTH(`DSP_B_MAXWIDTH),
+				.Y_WIDTH(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH),
+			) _TECHMAP_REPLACE_ (
 				.A(Aext),
 				.B(Bext),
 				.Y(Y)