From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 16 Nov 2017 20:37:02 +0000 (+0100)
Subject: Add "synth_ice40 -vpr"
X-Git-Tag: yosys-0.8~274
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=234726c65537cf665681bf9af5bda6d57a90df23;p=yosys.git

Add "synth_ice40 -vpr"
---

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 0227ffadb..6550b75cf 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -27,6 +27,7 @@ module  \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (
 module  \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
 module  \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
 
+`ifndef NO_SB_LUT4
 module \$lut (A, Y);
   parameter WIDTH = 0;
   parameter LUT = 0;
@@ -55,3 +56,4 @@ module \$lut (A, Y);
     end
   endgenerate
 endmodule
+`endif
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index a49372c8a..57f96ca1a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -68,6 +68,10 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -abc2\n");
 		log("        run two passes of 'abc' for slightly improved logic density\n");
 		log("\n");
+		log("    -vpr\n");
+		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
+		log("        (this fueature is experimental and incomplete)\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -75,7 +79,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file;
-	bool nocarry, nobram, flatten, retime, abc2;
+	bool nocarry, nobram, flatten, retime, abc2, vpr;
 
 	virtual void clear_flags() YS_OVERRIDE
 	{
@@ -87,6 +91,7 @@ struct SynthIce40Pass : public ScriptPass
 		flatten = true;
 		retime = false;
 		abc2 = false;
+		vpr = false;
 	}
 
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -141,6 +146,10 @@ struct SynthIce40Pass : public ScriptPass
 				abc2 = true;
 				continue;
 			}
+			if (args[argidx] == "-vpr") {
+				vpr = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -201,7 +210,7 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			run("dffsr2dff");
 			run("dff2dffe -direct-match $_DFF_*");
-			run("techmap -map +/ice40/cells_map.v");
+			run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
@@ -222,7 +231,11 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (check_label("map_cells"))
 		{
-			run("techmap -map +/ice40/cells_map.v");
+			if (vpr)
+				run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v");
+			else
+				run("techmap -map +/ice40/cells_map.v", "(with -D NO_SB_LUT4 in vpr mode)");
+
 			run("clean");
 		}
 
@@ -235,8 +248,17 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (check_label("blif"))
 		{
-			if (!blif_file.empty() || help_mode)
-				run(stringf("write_blif -gates -attr -param %s", help_mode ? "<file-name>" : blif_file.c_str()));
+			if (!blif_file.empty() || help_mode) {
+				if (vpr || help_mode) {
+					run(stringf("opt_clean -purge"),
+							"                          (vpr mode)");
+					run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()),
+							"                    (vpr mode)");
+				}
+				if (!vpr)
+					run(stringf("write_blif -gates -attr -param %s",
+							help_mode ? "<file-name>" : blif_file.c_str()), "(non-vpr mode)");
+			}
 		}
 
 		if (check_label("edif"))