From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 25 Sep 2019 23:51:31 +0000 (-0700)
Subject: Remove _TECHMAP_CELLTYPE_ check since all $mul
X-Git-Tag: working-ls180~1039^2~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=234738b103d4f2b3d937ed928fd89bc4e31627f1;p=yosys.git

Remove _TECHMAP_CELLTYPE_ check since all $mul
---

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 25ff28ab5..8c6a836f8 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -61,8 +61,6 @@ module _80_mul (A, B, Y);
 	input [B_WIDTH-1:0] B;
 	output [Y_WIDTH-1:0] Y;
 
-	parameter _TECHMAP_CELLTYPE_ = "";
-
 	generate
 	if (0) begin end
 `ifdef DSP_A_MINWIDTH
@@ -77,10 +75,8 @@ module _80_mul (A, B, Y);
 	else if (Y_WIDTH < `DSP_Y_MINWIDTH)
 		wire _TECHMAP_FAIL_ = 1;
 `endif
-	else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)
-		wire _TECHMAP_FAIL_ = 1;
 `ifdef DSP_SIGNEDONLY
-	else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)
+	else if (!A_SIGNED)
 		\$mul #(
 			.A_SIGNED(1),
 			.B_SIGNED(1),
@@ -93,7 +89,7 @@ module _80_mul (A, B, Y);
 			.Y(Y)
 		);
 `endif
-	else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH)
+	else if (A_WIDTH < B_WIDTH)
 		\$mul #(
 			.A_SIGNED(B_SIGNED),
 			.B_SIGNED(A_SIGNED),