From: Ahmed Irfan Date: Sat, 18 Jan 2014 20:54:52 +0000 (+0100) Subject: script added X-Git-Tag: yosys-0.2.0~146^2~7^2~5 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=234d0d0e1c316d7253c56c522dcc982a5e6049a1;p=yosys.git script added --- diff --git a/btor.ys b/btor.ys index 65accc95c..7f3882b57 100644 --- a/btor.ys +++ b/btor.ys @@ -1,10 +1,3 @@ -#design should be loaded before executing -#set the: hierarchy -top -#set the: hierarchy -libdir - -#high level synthesis -################# -#converting processes to cells proc; opt; opt_const -mux_undef; opt; rename -hide;;; @@ -17,6 +10,6 @@ flatten;; memory_unpack; #cell output to be a single wire splitnets -driver; +setundef -zero -undriven; opt;;; -#writing btor -write_btor design.btor; + diff --git a/verilog2btor.sh b/verilog2btor.sh new file mode 100755 index 000000000..e01d15084 --- /dev/null +++ b/verilog2btor.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +# +# Script to writing btor from verilog design +# + +if [ "$#" -ne 3 ]; then + echo "Usage: $0 input.v output.btor top-module-name" >&2 + exit 1 +fi +if ! [ -e "$1" ]; then + echo "$1 not found" >&2 + exit 1 +fi + +FULL_PATH=$(readlink -f $1) +DIR=$(dirname $FULL_PATH) + +./yosys -p " +read_verilog $1; +hierarchy -top $3; +hierarchy -libdir $DIR; +hierarchy -check; +script btor.ys; +write_btor $2;" +