From: whitequark <whitequark@whitequark.org>
Date: Tue, 26 Jan 2021 18:29:16 +0000 (+0000)
Subject: flatten: clarify confusing error message.
X-Git-Tag: working-ls180~101^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2364820f504beef06d0d94d6b2e82eddffeb57c1;p=yosys.git

flatten: clarify confusing error message.
---

diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc
index ec5f83fb0..f35b7ff60 100644
--- a/passes/techmap/flatten.cc
+++ b/passes/techmap/flatten.cc
@@ -211,7 +211,7 @@ struct FlattenWorker
 			log_assert(new_conn.first.size() == new_conn.second.size());
 
 			if (sigmap(new_conn.first).has_const())
-				log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
+				log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n",
 					log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second));
 
 			module->connect(new_conn);