From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 13 May 2020 20:33:37 +0000 (-0700)
Subject: verilog: default to input in sv mode if task/func has no dir ...
X-Git-Tag: working-ls180~554^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=237962debd9fcb7e9fb45f53bc8a53f0c34d9888;p=yosys.git

verilog: default to input in sv mode if task/func has no dir ...

otherwise error
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index b7c6af91e..f250d7685 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -855,8 +855,16 @@ task_func_port:
 			frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
 	} wire_name |
 	{
-		if (!astbuf1)
-			frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported");
+		if (!astbuf1) {
+			if (!sv_mode)
+				frontend_verilog_yyerror("task/function argument direction missing");
+			albuf = new dict<IdString, AstNode*>;
+			astbuf1 = new AstNode(AST_WIRE);
+			current_wire_rand = false;
+			current_wire_const = false;
+			astbuf1->is_input = true;
+			astbuf2 = NULL;
+		}
 	} wire_name;
 
 task_func_body: