From: Luke Kenneth Casson Leighton Date: Tue, 18 Jan 2022 15:57:39 +0000 (+0000) Subject: add getting of "fast" SPRs over DMI interface X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2385c1ce0f05d333626a2a6a0d0eddf4cabe51e6;p=libresoc-litex.git add getting of "fast" SPRs over DMI interface decrementer test is getting corrupted SRR1 and needs investigating --- diff --git a/sim.py b/sim.py index c4d1b9d..3a74235 100755 --- a/sim.py +++ b/sim.py @@ -60,12 +60,12 @@ class LibreSoCSim(SoCSDRAM): # "micropython/firmware.bin" #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ # "tests/xics/xics.bin" - #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ - # "tests/decrementer/decrementer.bin" + ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ + "tests/decrementer/decrementer.bin" #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ # "hello_world/hello_world.bin" - ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ - "tests/mmu/mmu.bin" + #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ + # "tests/mmu/mmu.bin" #ram_fname = None # reserve XICS ICP and XICS memory addresses. @@ -209,6 +209,7 @@ class LibreSoCSim(SoCSDRAM): # debug log out dbg_addr = Signal(4) + regnum = Signal(6) dbg_dout = Signal(64) dbg_msg = Signal(1) @@ -314,8 +315,23 @@ class LibreSoCSim(SoCSDRAM): Display(" xer: so %d ca %d 32 %d ov %d 32 %d", xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32), ), - If(dbg_addr == 0b101, # GPR - Display(" gpr: %016x", dbg_dout), + If(dbg_addr == 0b101, # GPRs (and "fast" SPRs) + If(regnum <= 31, Display(" gpr%02x: %016x", + regnum, dbg_dout),), # GPRs + If(regnum == 32, Display(" LR: %016x", dbg_dout),), # LR + If(regnum == 33, Display(" CTR: %016x", dbg_dout),), # CTR + If(regnum == 34, Display(" SRR0: %016x", dbg_dout),), # SRR0 + If(regnum == 35, Display(" SRR1: %016x", dbg_dout),), # SRR1 + If(regnum == 36, Display(" HSRR0: %016x", dbg_dout),), # HSRR0 + If(regnum == 37, Display(" HSRR1: %016x", dbg_dout),), # HSRR1 + If(regnum == 38, Display(" SPRG0: %016x", dbg_dout),), # SPRG0 + If(regnum == 39, Display(" SPRG1: %016x", dbg_dout),), # SPRG1 + If(regnum == 40, Display(" SPRG2: %016x", dbg_dout),), # SPRG2 + If(regnum == 41, Display(" SPRG3: %016x", dbg_dout),), # SPRG3 + If(regnum == 42, Display(" HSPRG0: %016x", dbg_dout),), # HSPRG0 + If(regnum == 43, Display(" HSPRG1: %016x", dbg_dout),), # HSPRG1 + If(regnum == 44, Display(" XER: %016x", dbg_dout),), # XER + If(regnum == 45, Display(" TAR: %016x", dbg_dout),), # TAR ), # also check if this is a "stat" If(dbg_addr == 1, # requested a STAT @@ -373,7 +389,6 @@ class LibreSoCSim(SoCSDRAM): #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58)) self.comb += active_dbg.eq(1) - # get the MSR self.sync += If(active_dbg & (dmicount == 12), (dmi_addr.eq(0b11), # MSR @@ -397,7 +412,7 @@ class LibreSoCSim(SoCSDRAM): #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c)) self.comb += active_dbg_xer.eq(active_dbg_cr) - # get the CR + # get the XER self.sync += If(active_dbg_xer & (dmicount == 20), (dmi_addr.eq(0b1001), # XER dmi_req.eq(1), @@ -405,11 +420,13 @@ class LibreSoCSim(SoCSDRAM): ) ) - # read all 32 GPRs - for i in range(32): + # read all 32 GPRs plus the next 16 which in microwatt are + # the "fast" SPRs, LR, CTR, SRR0, SRR1, etc. + for i in range(48): self.sync += If(active_dbg & (dmicount == 24+(i*8)), (dmi_addr.eq(0b100), # GSPR addr - dmi_din.eq(i), # r1 + dmi_din.eq(i), # register number (0-31 GPR, 32-48 fast SPRs) + regnum.eq(i), dmi_req.eq(1), dmi_wen.eq(1), )