From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 16 Jun 2019 06:10:31 +0000 (+0100)
Subject: add elaboratables
X-Git-Tag: ls180-24jan2020~990
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2387f838fe6928dc8a60ffbc85d4197579433fc0;p=ieee754fpu.git

add elaboratables
---

diff --git a/src/ieee754/fpadd/fadd_state.py b/src/ieee754/fpadd/fadd_state.py
index 450af3c1..5601da36 100644
--- a/src/ieee754/fpadd/fadd_state.py
+++ b/src/ieee754/fpadd/fadd_state.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat
+from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
@@ -11,7 +11,7 @@ from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
 from nmutil.nmoperator import eq
 
 
-class FPADD(FPBase):
+class FPADD(FPBase, Elaboratable):
 
     def __init__(self, width, single_cycle=False):
         FPBase.__init__(self)
diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py
index 4c136544..918e35a2 100644
--- a/src/ieee754/fpadd/statemachine.py
+++ b/src/ieee754/fpadd/statemachine.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
+from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
@@ -46,7 +46,7 @@ class FPOpData:
         return list(self)
 
 
-class FPADDBaseMod:
+class FPADDBaseMod(Elaboratable):
 
     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
         """ IEEE754 FP Add
@@ -268,7 +268,7 @@ class FPADDBase(FPState):
                 m.d.sync += self.out_z.stb.eq(1)
 
 
-class FPADD(FPID):
+class FPADD(FPID, Elaboratable):
     """ FPADD: stages as follows:
 
         FPGetOp (a)