From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 22:28:56 +0000 (+0100)
Subject: munge/redirect the regfile port based on the naming
X-Git-Tag: div_pipeline~624
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=23904c2b4fc41363339049c1b8743c25ac7234a9;p=soc.git

munge/redirect the regfile port based on the naming
"full" ports are the first indexed.
also only enable the read-port enable if the picker is enabled
---

diff --git a/src/soc/scoremulti/fu_fu_matrix.py b/src/soc/scoremulti/fu_fu_matrix.py
index d86043ba..8e2de10e 100644
--- a/src/soc/scoremulti/fu_fu_matrix.py
+++ b/src/soc/scoremulti/fu_fu_matrix.py
@@ -158,7 +158,7 @@ def d_matrix_sim(dut):
     yield
 
 def test_fu_fu_matrix():
-    dut = FUFUDepMatrix(n_fu_row=4, n_fu_col=4, n_src=3, n_dest=2)
+    dut = FUFUDepMatrix(n_fu_row=30, n_fu_col=30, n_src=3, n_dest=2)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_fu_fu_matrix.il", "w") as f:
         f.write(vl)
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index ff7f9277..cb212dfa 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -80,6 +80,16 @@ class NonProductionCore(Elaboratable):
         for regfile, spec in byregfiles_rd.items():
             rdpickers[regfile] = {}
             for rpidx, (idx, fuspec) in enumerate(spec.items()):
+                # get the regfile specs for this regfile port
+                (regname, rdflag, read, wid) = byregfiles_rdspec[regfile]
+
+                # "munge" the regfile port index, due to full-port access
+                if regfile in ['XER', 'CR']:
+                    if regname.startswith('full'):
+                        rpidx = 0 # by convention, first port
+                    else:
+                        rpidx += 1 # start indexing port 0 from 1
+
                 # select the required read port.  these are pre-defined sizes
                 print (regfile, regs.rf.keys())
                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
@@ -89,8 +99,8 @@ class NonProductionCore(Elaboratable):
                 setattr(m.submodules, "rdpick_%s_%d" % (regfile, idx), rdpick)
 
                 # connect the regspec "reg select" number to this port
-                (regname, rdflag, read, wid) = byregfiles_rdspec[regfile]
-                comb += rport.ren.eq(read)
+                with m.If(rdpick.en_o):
+                    comb += rport.ren.eq(read)
 
                 # connect up the FU req/go signals and the reg-read to the FU
                 for pi, (funame, fu) in enumerate(fuspec):