From: Stuart Olsen <stuart@sj-olsen.com>
Date: Tue, 7 Apr 2020 05:22:09 +0000 (-0700)
Subject: back.pysim: Reuse clock simulation commands
X-Git-Tag: working_23jun2020~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2398b792;p=nmigen.git

back.pysim: Reuse clock simulation commands
---

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 398266e..f0fa2da 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -1021,11 +1021,14 @@ class Simulator:
             # Behave correctly if the process is added after the clock signal is manipulated, or if
             # its reset state is high.
             initial = (yield domain.clk)
+            steps = (
+                domain.clk.eq(~initial),
+                Delay(half_period),
+                domain.clk.eq(initial),
+                Delay(half_period),
+            )
             while True:
-                yield domain.clk.eq(~initial)
-                yield Delay(half_period)
-                yield domain.clk.eq(initial)
-                yield Delay(half_period)
+                yield from iter(steps)
         self._add_coroutine_process(clk_process, default_cmd=None)
         self._clocked.add(domain)