From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 27 Aug 2016 15:06:22 +0000 (+0200)
Subject: Fixed handling of transparent bram rd ports on ROMs
X-Git-Tag: yosys-0.7~99
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=23afeadb5e01a7b816c6ae203746caa8ae2aaed7;p=yosys.git

Fixed handling of transparent bram rd ports on ROMs
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ad90965fb..72809d42d 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1482,6 +1482,7 @@ void RTLIL::Module::connect(const RTLIL::SigSig &conn)
 		log_backtrace("-X- ", yosys_xtrace-1);
 	}
 
+	log_assert(GetSize(conn.first) == GetSize(conn.second));
 	connections_.push_back(conn);
 }
 
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 7b5dd08ab..a7f9cf382 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -656,6 +656,9 @@ grow_read_ports:;
 		bool transp = rd_transp[cell_port_i] == State::S1;
 		SigBit clksig = rd_clk[cell_port_i];
 
+		if (wr_ports == 0)
+			transp = false;
+
 		pair<SigBit, bool> clkdom(clksig, clkpol);
 		if (!clken)
 			clkdom = pair<SigBit, bool>(State::S1, false);