From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 Jun 2018 04:01:50 +0000 (+0100)
Subject: reorg
X-Git-Tag: convert-csv-opcode-to-binary~5241
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=23c104e016a77047dd3653781763f4b2aa6f1ef1;p=libreriscv.git

reorg
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 994afb084..c156ed4ad 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -696,9 +696,7 @@ loop:
 
  \begin{itemize}
    \item Is C.FNE actually needed? Should it be added if it is?
-   \item Element type implies polymorphism.  Should it be in SV?
    \item Should use of registers be allowed to "wrap" (x30 x31 x1 x2)?
-   \item Is detection of all-scalar ops ok (without slowing pipeline)?
    \item Can VSELECT be removed? (it's really complex)
    \item Can CLIP be done as a CSR (mode, like elwidth)
    \item SIMD saturation (etc.) also set as a mode?