From: Claire Wolf <clifford@clifford.at>
Date: Thu, 30 Jan 2020 17:01:13 +0000 (+0100)
Subject: Add Verific support for OPER_REDUCE_NAND
X-Git-Tag: working-ls180~830^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=23c44afaed7c3fb97b01ca241731fc84dd03d5a7;p=yosys.git

Add Verific support for OPER_REDUCE_NAND

Signed-off-by: Claire Wolf <clifford@clifford.at>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9274cf5ca..8a99f19b9 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -539,6 +539,14 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		return true;
 	}
 
+	if (inst->Type() == OPER_REDUCE_NAND) {
+		Wire *tmp = module->addWire(NEW_ID);
+		cell = module->addReduceAnd(inst_name, IN, tmp, SIGNED);
+		module->addNot(NEW_ID, tmp, net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
+		return true;
+	}
+
 	if (inst->Type() == OPER_REDUCE_OR) {
 		cell = module->addReduceOr(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
 		import_attributes(cell->attributes, inst);