From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 4 Sep 2020 21:08:18 +0000 (+0100)
Subject: add multi-ported memory link
X-Git-Tag: convert-csv-opcode-to-binary~2183
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=23f13b4d748977f6d7ced969c56967c37fc5f7aa;p=libreriscv.git

add multi-ported memory link
---

diff --git a/resources.mdwn b/resources.mdwn
index 95f2c319f..72a59f648 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -328,6 +328,8 @@ Some learning resources I found in the community:
 * Efabless "Openlane" <https://github.com/efabless/openlane>
 * Co-simulation plugin for verilator, transferring to ECP5
   <https://github.com/vmware/cascade>
+* Multi-read/write ported memories
+  <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
 
 
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