From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Dec 2019 15:34:07 +0000 (-0800)
Subject: Make SV2017 compliant courtesy of @wsnyder
X-Git-Tag: working-ls180~915^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=23fcfd0adb51f800936b70999a5f95fe59ee7631;p=yosys.git

Make SV2017 compliant courtesy of @wsnyder
---

diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v
index 9bd38fcb3..88d0553b9 100644
--- a/tests/simple/mem_arst.v
+++ b/tests/simple/mem_arst.v
@@ -7,11 +7,9 @@ module MyMem #(
   input                  Clk_i,
   input  [AddrWidth-1:0] Addr_i,
   input  [DataWidth-1:0] Data_i,
-  output [DataWidth-1:0] Data_o,
+  output reg [DataWidth-1:0] Data_o,
   input                  WR_i);
 
-  reg [DataWidth-1:0] Data_o;
-
   localparam Size = 2**AddrWidth;
 
   (* mem2reg *)