From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 24 May 2019 16:51:26 +0000 (+0100)
Subject: make qlq output q | q_int
X-Git-Tag: ls180-24jan2020~998
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=23fdc49c72336f07af4d70744e931a637db8ee82;p=ieee754fpu.git

make qlq output q | q_int
---

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index 0833ae61..fd28cd4a 100644
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -37,11 +37,11 @@ class SRLatch(Elaboratable):
         self.r = Signal(reset=1) # defaults to off
         self.q = Signal(reset_less=True)
         self.qn = Signal(reset_less=True)
-        self.qlq = Signal()
+        self.qlq = Signal(reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
-        q_int = self.qlq
+        q_int = Signal()
 
         if self.sync:
             with m.If(self.s):
@@ -62,6 +62,7 @@ class SRLatch(Elaboratable):
                 m.d.sync += q_int.eq(q_int)
                 m.d.comb += self.q.eq(q_int)
         m.d.comb += self.qn.eq(~self.q)
+        m.d.comb += self.qlq.eq(self.q | q_int) # useful output
 
         return m