From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Thu, 27 May 2021 18:55:09 +0000 (+0200)
Subject: proc_memwr: Use the v2 memwr cell.
X-Git-Tag: yosys-0.10~52
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24027b5446ffa9d47e00e2ab8bc773fdebc246bd;p=yosys.git

proc_memwr: Use the v2 memwr cell.
---

diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc
index f898979d8..cf10bd4b2 100644
--- a/passes/proc/proc_memwr.cc
+++ b/passes/proc/proc_memwr.cc
@@ -29,17 +29,26 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &next_priority)
+void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &next_port_id)
 {
 	for (auto sr : proc->syncs)
 	{
+		std::vector<int> prev_port_ids;
 		for (auto memwr : sr->mem_write_actions) {
-			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr));
+			int port_id = next_port_id[memwr.memid]++;
+			Const priority_mask(State::S0, port_id);
+			for (int i = 0; i < GetSize(prev_port_ids); i++)
+				if (memwr.priority_mask[i] == State::S1)
+					priority_mask[prev_port_ids[i]] = State::S1;
+			prev_port_ids.push_back(port_id);
+
+			RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));
 			cell->attributes = memwr.attributes;
 			cell->setParam(ID::MEMID, Const(memwr.memid.str()));
 			cell->setParam(ID::ABITS, GetSize(memwr.address));
 			cell->setParam(ID::WIDTH, GetSize(memwr.data));
-			cell->setParam(ID::PRIORITY, next_priority[memwr.memid]++);
+			cell->setParam(ID::PORTID, port_id);
+			cell->setParam(ID::PRIORITY_MASK, priority_mask);
 			cell->setPort(ID::ADDR, memwr.address);
 			cell->setPort(ID::DATA, memwr.data);
 			SigSpec enable = memwr.enable;
@@ -91,18 +100,19 @@ struct ProcMemWrPass : public Pass {
 		extra_args(args, 1, design);
 
 		for (auto module : design->selected_modules()) {
-			dict<IdString, int> next_priority;
+			dict<IdString, int> next_port_id;
 			for (auto cell : module->cells()) {
-				if (cell->type == ID($memwr)) {
+				if (cell->type.in(ID($memwr), ID($memwr_v2))) {
+					bool is_compat = cell->type == ID($memwr);
 					IdString memid = cell->parameters.at(ID::MEMID).decode_string();
-					int priority = cell->parameters.at(ID::PRIORITY).as_int();
-					if (priority >= next_priority[memid])
-						next_priority[memid] = priority + 1;
+					int port_id = cell->parameters.at(is_compat ? ID::PRIORITY : ID::PORTID).as_int();
+					if (port_id >= next_port_id[memid])
+						next_port_id[memid] = port_id + 1;
 				}
 			}
 			for (auto &proc_it : module->processes)
 				if (design->selected(module, proc_it.second))
-					proc_memwr(module, proc_it.second, next_priority);
+					proc_memwr(module, proc_it.second, next_port_id);
 		}
 	}
 } ProcMemWrPass;
diff --git a/tests/opt/bug2765.ys b/tests/opt/bug2765.ys
index fef9abb02..7cb790bd7 100644
--- a/tests/opt/bug2765.ys
+++ b/tests/opt/bug2765.ys
@@ -29,6 +29,6 @@ EOT
 
 proc
 opt
-select -assert-count 2 t:$memwr
+select -assert-count 2 t:$memwr_v2
 opt_mem
 select -assert-count 1 t:$memwr_v2
diff --git a/tests/opt/opt_clean_mem.ys b/tests/opt/opt_clean_mem.ys
index 5e85df6c8..71f9e0d7b 100644
--- a/tests/opt/opt_clean_mem.ys
+++ b/tests/opt/opt_clean_mem.ys
@@ -24,25 +24,25 @@ EOT
 proc
 
 select -assert-count 2 t:$memrd
-select -assert-count 1 t:$memwr
+select -assert-count 1 t:$memwr_v2
 select -assert-count 1 t:$meminit_v2
 design -save orig
 
 opt_clean
 select -assert-none t:$memrd
-select -assert-none t:$memwr
+select -assert-none t:$memwr_v2
 select -assert-none t:$meminit_v2
 
 design -load orig
 expose top/rd1
 opt_clean
 select -assert-count 1 t:$memrd
-select -assert-count 1 t:$memwr
+select -assert-count 1 t:$memwr_v2
 select -assert-count 1 t:$meminit_v2
 
 design -load orig
 expose top/rd1 top/rd2
 opt_clean
 select -assert-count 2 t:$memrd
-select -assert-count 1 t:$memwr
+select -assert-count 1 t:$memwr_v2
 select -assert-count 1 t:$meminit_v2