From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Sun, 12 Jul 2020 13:39:40 +0000 (+0200)
Subject: dfflegalize: Gather init values from all wires.
X-Git-Tag: working-ls180~389
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=240351c44ecadc3a5c67b298568a04373883eca5;p=yosys.git

dfflegalize: Gather init values from all wires.

Skipping non-selected wires is unsound in an obvious way.
---

diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc
index c0f112836..13ce4f49a 100644
--- a/passes/techmap/dfflegalize.cc
+++ b/passes/techmap/dfflegalize.cc
@@ -1296,7 +1296,7 @@ unrecognized:
 			sigmap.set(module);
 			initbits.clear();
 
-			for (auto wire : module->selected_wires())
+			for (auto wire : module->wires())
 			{
 				if (wire->attributes.count(ID::init) == 0)
 					continue;