From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 26 Nov 2012 17:19:10 +0000 (+0100)
Subject: examples/sim/memory: do not use MemoryPort
X-Git-Tag: 24jan2021_ls180~2099^2~753
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2418367c7a7e834243dbfd78aebbee90d105795c;p=litex.git

examples/sim/memory: do not use MemoryPort
---

diff --git a/examples/sim/memory.py b/examples/sim/memory.py
index 34ae1126..1b1e67c7 100644
--- a/examples/sim/memory.py
+++ b/examples/sim/memory.py
@@ -7,12 +7,9 @@ from migen.sim.icarus import Runner
 
 class Mem:
 	def __init__(self):
-		self.a = Signal(BV(12))
-		self.d = Signal(BV(16))
-		p = MemoryPort(self.a, self.d)
 		# Initialize the beginning of the memory with integers
 		# from 0 to 19.
-		self.mem = Memory(16, 2**12, p, init=list(range(20)))
+		self.mem = Memory(16, 2**12, init=list(range(20)))
 	
 	def do_simulation(self, s):
 		# Read the memory. Use the cycle counter as address.