From: Cesar Strauss <cestrauss@gmail.com>
Date: Wed, 17 Feb 2021 12:18:53 +0000 (-0300)
Subject: Add a case for checking the EXTRA field and register augmenting
X-Git-Tag: convert-csv-opcode-to-binary~223
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=242a08349c9b04d3eb7a4d072de6664d9b729f25;p=soc.git

Add a case for checking the EXTRA field and register augmenting

By carefully choosing unique v3.0b register numbers and Extra field
patterns, any mistake in encoding and decoding will likely be caught.
---

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index ad692243..73e8955f 100644
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -50,3 +50,28 @@ class SVP64ALUTestCase(TestAccumulatorBase):
 
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
+
+    # This case helps checking the encoding of the Extra field
+    # It was built so the v3.0b registers are: 3, 2, 1
+    # and the Extra field is: 101.110.111
+    # The expected SVP64 register numbers are: 13, 10, 7
+    # Any mistake in decoding will probably give a different answer
+    def case_3_sv_check_extra(self):
+        # adds:
+        #       13 = 10 + 7   => 0x4242 = 0x1230 + 0x3012
+        isa = SVP64Asm(['sv.add 13.v, 10.v, 7.v'])
+        lst = list(isa)
+        print("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[7] = 0x3012
+        initial_regs[10] = 0x1230
+        svstate = SVP64State()
+        # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
+        svstate.vl[0:7] = 1  # VL
+        svstate.maxvl[0:7] = 1  # MAXVL
+        print("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)