From: Eddie Hung Date: Fri, 23 Aug 2019 20:06:31 +0000 (-0700) Subject: Cope with possibility that D could connect to Q on same cell X-Git-Tag: working-ls180~1085^2~45 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=242b3083eac817c927624db735ca3196223f97c0;p=yosys.git Cope with possibility that D could connect to Q on same cell --- diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index fffff91e8..5d74b91bc 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -197,7 +197,7 @@ match next select !next->has_keep_attr() select !port(next, \D)[0].wire->get_bool_attribute(\keep) slice idx GetSize(port(next, \Q)) - select nusers(port(next, \Q)[idx]) == 3 + select nusers(port(next, \Q)[idx]) <= 3 index next->type === chain.back().first->type index port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second] index port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]