From: Eddie Hung Date: Fri, 21 Jun 2019 02:37:03 +0000 (-0700) Subject: Fix simple_abc9/generate test with 1'bx at MSB X-Git-Tag: working-ls180~1208^2~127 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=242b72d4e11b815d0ca4fa80eee2e112333608d2;p=yosys.git Fix simple_abc9/generate test with 1'bx at MSB --- diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f652cdf12..3f7efa800 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -492,7 +492,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (w->port_output) { RTLIL::Wire *wire = module->wire(w->name); log_assert(wire); - for (int i = 0; i < GetSize(wire); i++) + for (int i = 0; i < GetSize(w); i++) output_bits.insert({wire, i}); } }