From: Luke Kenneth Casson Leighton Date: Wed, 25 Mar 2020 15:53:02 +0000 (+0000) Subject: Re: [libre-riscv-dev] cache SRAM organisation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=242e45d28d34fe047ecaf552b04a4e1a8b0e4909;p=libre-riscv-dev.git Re: [libre-riscv-dev] cache SRAM organisation --- diff --git a/b2/2e60284079bc5893ad4808e65311443b93b2ca b/b2/2e60284079bc5893ad4808e65311443b93b2ca new file mode 100644 index 0000000..2be35c5 --- /dev/null +++ b/b2/2e60284079bc5893ad4808e65311443b93b2ca @@ -0,0 +1,131 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 25 Mar 2020 15:53:40 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jH8Lb-0000nd-Nd; Wed, 25 Mar 2020 15:53:39 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jH8La-0000nX-3S + for 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