From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 10 Sep 2022 14:31:05 +0000 (+0100)
Subject: reduce pagesize, include links inline
X-Git-Tag: opf_rfc_ls005_v1~516
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=243447e0ccfa15c4b83d926b3fdfa78141a6b9c8;p=libreriscv.git

reduce pagesize, include links inline
---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 7f16d17f0..d8aa2ce81 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -1,11 +1,9 @@
 # OPF ISA WG External RFC LS001 08Sep2022
 
+* Author: Luke Kenneth Casson Leighton.
+* Contributors/Ideas: Brad Frey, Paul Mackerras
 * <https://git.openpower.foundation/isa/PowerISA/issues/64> 
   [[ls001/discussion]]
-* <https://libre-soc.org/openpower/sv/int_fp_mv>
-* <https://libre-soc.org/openpower/sv/fclass/>
-* <https://libre-soc.org/openpower/sv/fcvt/>
-* <https://libre-soc.org/openpower/sv/cr_int_predication/>
 
 This proposal is to extend the Power ISA with an Abstract RISC-Paradigm
 Vectorisation Concept that may be applied to **all and any** suitable
@@ -40,7 +38,14 @@ cryptographic
 [bitmanipulation](https://libre-soc.org/openpower/sv/bitmanip)
 operations that ARM
 Intel AMD and many other ISAs have been adding over the past 12 years
-and Power ISA has not.
+and Power ISA has not.  Three additional FP-related sets are needed
+(missing from SFFS) -
+[int_fp_mv](https://libre-soc.org/openpower/sv/int_fp_mv/)
+[fclass](https://libre-soc.org/openpower/sv/fclass/) and
+[fcvt](https://libre-soc.org/openpower/sv/fcvt/)
+and one set named
+[crweird](https://libre-soc.org/openpower/sv/cr_int_predication/)
+increase the capability of CR Fields.
 
 *Thus it becomes necesary to consider the Architectural Resource
 Allocation of not just Simple-V but the 80-100 Scalar instructions all
@@ -185,7 +190,8 @@ The primary options are:
   be saturated (without adding explicit scalar saturated opcodes)
 * Reduction and Prefix-Sum (Fibonnacci Series) Modes
 
-# REMAP subsystem
+\newpage{}
+# Simple-V REMAP subsystem
 
 REMAP is extremely advanced but brings features already present in other
 DSPs and Supercomputing ISAs.
@@ -214,7 +220,8 @@ in the *general purpose* compute area in the past 12 years, that some
 considerable care is needed.
 
 Summary:
-**to fit everything at least 75% of 3 separate Major Opcodes is required**
+**Including Simple-V, to fit everything at least 75% of 3 separate
+Major Opcodes would be required**
 
 Candidates (for all but the X-Form instructions) include: