From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon, 25 Jan 2016 23:00:38 +0000 (-0800)
Subject: i965/fs: Feel free to spill partial reads/writes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2434ceabf41e66f2a3627ea8591e5ca427a78cce;p=mesa.git

i965/fs: Feel free to spill partial reads/writes

Now that we properly handle write-masking, this should be safe.
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 791da0e038e..8396854fcb1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -808,30 +808,13 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
     */
    foreach_block_and_inst(block, fs_inst, inst, cfg) {
       for (unsigned int i = 0; i < inst->sources; i++) {
-	 if (inst->src[i].file == VGRF) {
+	 if (inst->src[i].file == VGRF)
             spill_costs[inst->src[i].nr] += loop_scale;
-
-            /* Register spilling logic assumes full-width registers; smeared
-             * registers have a width of 1 so if we try to spill them we'll
-             * generate invalid assembly.  This shouldn't be a problem because
-             * smeared registers are only used as short-term temporaries when
-             * loading pull constants, so spilling them is unlikely to reduce
-             * register pressure anyhow.
-             */
-            if (!inst->src[i].is_contiguous()) {
-               no_spill[inst->src[i].nr] = true;
-            }
-	 }
       }
 
-      if (inst->dst.file == VGRF) {
+      if (inst->dst.file == VGRF)
          spill_costs[inst->dst.nr] += inst->regs_written * loop_scale;
 
-         if (!inst->dst.is_contiguous()) {
-            no_spill[inst->dst.nr] = true;
-         }
-      }
-
       switch (inst->opcode) {
 
       case BRW_OPCODE_DO: