From: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Date: Sat, 31 Jul 2021 22:43:26 +0000 (+0200)
Subject: Rename test_dcache, which can't be invoked by test runners
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=243e80326b06379a3214792f876d741ecf113fe1;p=soc.git

Rename test_dcache, which can't be invoked by test runners

Functions named *test_* are invoked by test runners, such as nosetests,
but test_dcache was not written with this behavior in mind. Rename it to
avoid invocation.

Maybe the main block at the end of a file should now be converted into a
test that *is* invoked by test runners.
---

diff --git a/src/soc/experiment/test/test_dcache.py b/src/soc/experiment/test/test_dcache.py
index fa4fa417..3212bad6 100644
--- a/src/soc/experiment/test/test_dcache.py
+++ b/src/soc/experiment/test/test_dcache.py
@@ -245,7 +245,7 @@ def dcache_sim(dut, mem):
     yield
 
 
-def test_dcache(mem, test_fn, test_name):
+def tst_dcache(mem, test_fn, test_name):
     dut = DCache()
 
     memory = Memory(width=64, depth=len(mem), init=mem, simulate=True)
@@ -311,18 +311,18 @@ if __name__ == '__main__':
     for i in range(memsize):
         mem.append(i)
 
-    test_dcache(mem, dcache_regression_sim, "simpleregression")
+    tst_dcache(mem, dcache_regression_sim, "simpleregression")
 
     mem = []
     memsize = 256
     for i in range(memsize):
         mem.append(i)
 
-    test_dcache(mem, dcache_random_sim, "random")
+    tst_dcache(mem, dcache_random_sim, "random")
 
     mem = []
     for i in range(1024):
         mem.append((i*2)| ((i*2+1)<<32))
 
-    test_dcache(mem, dcache_sim, "")
+    tst_dcache(mem, dcache_sim, "")
 
diff --git a/src/soc/experiment/test/test_dcache_tlb.py b/src/soc/experiment/test/test_dcache_tlb.py
index 3f32a281..835f4b27 100644
--- a/src/soc/experiment/test/test_dcache_tlb.py
+++ b/src/soc/experiment/test/test_dcache_tlb.py
@@ -276,7 +276,7 @@ def dcache_sim(dut, mem):
     yield
 
 
-def test_dcache(mem, test_fn, test_name):
+def tst_dcache(mem, test_fn, test_name):
     dut = DCache()
 
     memory = Memory(width=64, depth=len(mem), init=mem, simulate=True)
@@ -350,18 +350,18 @@ if __name__ == '__main__':
         for i in range(memsize):
             mem.append(i)
 
-        test_dcache(mem, dcache_regression_sim, "simpleregression")
+        tst_dcache(mem, dcache_regression_sim, "simpleregression")
 
         mem = []
         memsize = 256
         for i in range(memsize):
             mem.append(i)
 
-        test_dcache(mem, dcache_random_sim, "random")
+        tst_dcache(mem, dcache_random_sim, "random")
 
     mem = []
     for i in range(1024):
         mem.append((i*2)| ((i*2+1)<<32))
 
-    test_dcache(mem, dcache_sim, "")
+    tst_dcache(mem, dcache_sim, "")
 
diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py
index ec435e65..3dde127f 100644
--- a/src/soc/experiment/test/test_l0_cache_buffer2.py
+++ b/src/soc/experiment/test/test_l0_cache_buffer2.py
@@ -55,7 +55,7 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
         # TODO: memory ports
 
 
-def test_cache_single_run(dut):
+def tst_cache_single_run(dut):
     #test single byte
     addr = 0
     data = 0xfeedface
@@ -65,7 +65,7 @@ def test_cache_single():
     dut = TestCachedMemoryPortInterface()
     #LDSTSplitter(8, 48, 4) #data leng in bytes, address bits, select bits
 
-    run_simulation(dut, test_cache_single_run(dut),
+    run_simulation(dut, tst_cache_single_run(dut),
                    vcd_name='test_cache_single.vcd')