From: lkcl Date: Sat, 20 Aug 2022 12:44:42 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~824 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=243fc5505eb0f8d05510db6d5a3745fd9642532e;p=libreriscv.git --- diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index ad03600fd..80c6e7eac 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -321,14 +321,17 @@ and manual reordering of the Vector of RB offsets. # LD/ST ffirst -LD/ST ffirst treats the first LD/ST in a vector (element 0) as an -ordinary one. Exceptions, if any are needed occur "as normal" exactly as -they would on any Scalar v3.0 Power ISA LD/ST. However for elements 1 +LD/ST ffirst treats the first LD/ST in a vector (element 0 if REMAP +is not active) as an +ordinary one, with all behaviour with respect to Interrupts Exceptions +Page Faults Memory Management being identical in every regard to Scalar +v3.0 Power ISA LD/ST. However for elements 1 and above, if an exception would occur, then VL is **truncated** to the previous element: the exception is **not** then raised because the -LD/ST that would otherwise have caused an exception is *required* to be cancelled. +LD/ST that would otherwise have caused an exception is *required* to be cancelled. Additionally an implementor may choose to truncate VL for +any arbitrary reason *except for the very first*. -ffirst LD/ST to multiple pages via a Vectorised Index base is considered a security risk due to the abuse of probing multiple pages in rapid succession and getting feedback on which pages would fail. Therefore Vector Indexed LD/ST is prohibited entirely, and the Mode bit instead used for element-strided LD/ST. See +ffirst LD/ST to multiple pages via a Vectorised Index base is considered a security risk due to the abuse of probing multiple pages in rapid succession and getting speculative feedback on which pages would fail. Therefore Vector Indexed LD/ST is prohibited entirely, and the Mode bit instead used for element-strided LD/ST. See for(i = 0; i < VL; i++) reg[rt + i] = mem[reg[ra] + i * reg[rb]];