From: Marek Olšák Date: Fri, 14 Jun 2019 01:29:47 +0000 (-0400) Subject: radeonsi/gfx10: cosmetic changes X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=244a8e6798242427cc478a741d4b610c7eb2f954;p=mesa.git radeonsi/gfx10: cosmetic changes Acked-by: Bas Nieuwenhuizen --- diff --git a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c index 28da7b92250..c25a5b270c1 100644 --- a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c +++ b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c @@ -797,7 +797,7 @@ void si_build_prim_discard_compute_shader(struct si_shader_context *ctx) count = LLVMBuildMul(builder, count, LLVMConstInt(ctx->i32, vertices_per_prim, 0), ""); - /* VI needs to disable caching, so that the CP can see the stored value. + /* GFX8 needs to disable caching, so that the CP can see the stored value. * MTYPE=3 bypasses TC L2. */ if (ctx->screen->info.chip_class <= GFX8) { @@ -1196,6 +1196,8 @@ void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx, /* This needs to be done at the beginning of IBs due to possible * TTM buffer moves in the kernel. + * + * TODO: update for GFX10 */ si_emit_surface_sync(sctx, cs, S_0085F0_TC_ACTION_ENA(1) | diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 591986c30a6..5f34668ba4d 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -391,7 +391,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, } state[7] = meta_va >> 16; - } else if (sscreen->info.chip_class >= GFX9) { + } else if (sscreen->info.chip_class == GFX9) { state[3] &= C_008F1C_SW_MODE; state[4] &= C_008F20_PITCH; @@ -2109,7 +2109,7 @@ void si_shader_change_notify(struct si_context *sctx) if (sctx->chip_class >= GFX10) { si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_HS_0); - } else if (sctx->chip_class >= GFX9) { + } else if (sctx->chip_class == GFX9) { si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B430_SPI_SHADER_USER_DATA_LS_0); } else { diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index be3b897c791..27a5aa3b5ee 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -5225,7 +5225,7 @@ static bool si_shader_binary_open(struct si_screen *screen, if (sel && screen->info.chip_class >= GFX9 && sel->type == PIPE_SHADER_GEOMETRY && !shader->is_gs_copy_shader) { - esgs_ring_size = shader->gs_info.esgs_ring_size;; + esgs_ring_size = shader->gs_info.esgs_ring_size; } if (sel && shader->key.as_ngg) { @@ -5236,8 +5236,8 @@ static bool si_shader_binary_open(struct si_screen *screen, } /* GS stores Primitive IDs into LDS at the address corresponding - * to the provoking vertex. All vertex threads load and export - * PrimitiveID for their thread. + * to the ES thread of the provoking vertex. All ES threads + * load and export PrimitiveID for their thread. */ if (sel->type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id) @@ -6076,12 +6076,10 @@ static bool si_compile_tgsi_main(struct si_shader_context *ctx) ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in; if (shader->key.as_es) ctx->abi.emit_outputs = si_llvm_emit_es_epilogue; - else { - if (shader->key.as_ngg) - ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue; - else - ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue; - } + else if (shader->key.as_ngg) + ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue; + else + ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue; bld_base->emit_epilogue = si_tgsi_emit_epilogue; break; case PIPE_SHADER_GEOMETRY: diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 27e42d8cef9..c96f7afc1be 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2579,7 +2579,7 @@ static void si_initialize_color_surface(struct si_context *sctx, surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) | S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) | S_028EE0_RESOURCE_LEVEL(1); - } else if (sctx->chip_class >= GFX9) { + } else if (sctx->chip_class == GFX9) { color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level); color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) | S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type); @@ -3245,7 +3245,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb->cb_color_attrib2); radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3); - } else if (sctx->chip_class >= GFX9) { + } else if (sctx->chip_class == GFX9) { struct gfx9_surf_meta_flags meta; if (tex->dcc_offset) @@ -3380,7 +3380,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */ radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */ radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */ - } else if (sctx->chip_class >= GFX9) { + } else if (sctx->chip_class == GFX9) { radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3); radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */ radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */ @@ -3908,7 +3908,7 @@ gfx10_make_texture_descriptor(struct si_screen *screen, /* * X24S8 is implemented as an 8_8_8_8 data format, to * fix texture gathers. This affects at least - * GL45-CTS.texture_cube_map_array.sampling on VI. + * GL45-CTS.texture_cube_map_array.sampling on GFX8. */ util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle); is_stencil = true; @@ -4188,7 +4188,7 @@ si_make_texture_descriptor(struct si_screen *screen, } /* S8 with Z32 HTILE needs a special format. */ - if (screen->info.chip_class >= GFX9 && + if (screen->info.chip_class == GFX9 && pipe_format == PIPE_FORMAT_S8_UINT && tex->tc_compatible_htile) data_format = V_008F14_IMG_DATA_FORMAT_S8_32; @@ -4240,7 +4240,7 @@ si_make_texture_descriptor(struct si_screen *screen, state[6] = 0; state[7] = 0; - if (screen->info.chip_class >= GFX9) { + if (screen->info.chip_class == GFX9) { unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle); /* Depth is the the last accessible layer on Gfx9. @@ -4282,7 +4282,7 @@ si_make_texture_descriptor(struct si_screen *screen, va = tex->buffer.gpu_address + tex->fmask_offset; #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f))) - if (screen->info.chip_class >= GFX9) { + if (screen->info.chip_class == GFX9) { data_format = V_008F14_IMG_DATA_FORMAT_FMASK; switch (FMASK(res->nr_samples, res->nr_storage_samples)) { case FMASK(2,1): @@ -4391,7 +4391,7 @@ si_make_texture_descriptor(struct si_screen *screen, fmask_state[6] = 0; fmask_state[7] = 0; - if (screen->info.chip_class >= GFX9) { + if (screen->info.chip_class == GFX9) { fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode); fmask_state[4] |= S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch); @@ -5470,7 +5470,7 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0); si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0); - } else if (sctx->chip_class >= GFX9) { + } else if (sctx->chip_class == GFX9) { si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0); si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 2f142bc6781..fdde6b08310 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -697,7 +697,7 @@ static void si_emit_ia_multi_vgt_param(struct si_context *sctx, /* Draw state. */ if (ia_multi_vgt_param != sctx->last_multi_vgt_param) { - if (sctx->chip_class >= GFX9) + if (sctx->chip_class == GFX9) radeon_set_uconfig_reg_idx(cs, sctx->screen, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param); @@ -1015,7 +1015,9 @@ void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs, bool compute_ib = !sctx->has_graphics || cs == sctx->prim_discard_compute_cs; - if (sctx->chip_class >= GFX9 || compute_ib) { + assert(sctx->chip_class <= GFX9); + + if (sctx->chip_class == GFX9 || compute_ib) { /* Flush caches and wait for the caches to assert idle. */ radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0)); radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ @@ -1379,7 +1381,7 @@ void si_emit_cache_flush(struct si_context *sctx) /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't * wait for idle on GFX9. We have to use a TS event. */ - if (sctx->chip_class >= GFX9 && flush_cb_db) { + if (sctx->chip_class == GFX9 && flush_cb_db) { uint64_t va; unsigned tc_flags, cb_db_event;