From: Claire Wolf <claire@symbioticeda.com>
Date: Tue, 14 Jul 2020 22:04:23 +0000 (+0200)
Subject: Fix bison warnings for missing %empty
X-Git-Tag: working-ls180~380^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24540291c7b3b42518dfbea9ec59c9b681d0e54e;p=yosys.git

Fix bison warnings for missing %empty

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ba2eab3d3..390ef07e9 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -333,7 +333,7 @@ design:
 	typedef_decl design |
 	package design |
 	interface design |
-	/* empty */;
+	%empty;
 
 attr:
 	{
@@ -355,7 +355,7 @@ attr_opt:
 	attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
 		SET_RULE_LOC(@$, @2, @$);
 	}|
-	/* empty */;
+	%empty;
 
 defattr:
 	DEFATTR_BEGIN {
@@ -376,7 +376,7 @@ defattr:
 	} DEFATTR_END;
 
 opt_attr_list:
-	attr_list | /* empty */;
+	attr_list | %empty;
 
 attr_list:
 	attr_assign |
@@ -449,13 +449,13 @@ module:
 	};
 
 module_para_opt:
-	'#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */;
+	'#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | %empty;
 
 module_para_list:
 	single_module_para | module_para_list ',' single_module_para;
 
 single_module_para:
-	/* empty */ |
+	%empty |
 	attr TOK_PARAMETER {
 		if (astbuf1) delete astbuf1;
 		astbuf1 = new AstNode(AST_PARAMETER);
@@ -471,13 +471,13 @@ single_module_para:
 	single_param_decl;
 
 module_args_opt:
-	'(' ')' | /* empty */ | '(' module_args optional_comma ')';
+	'(' ')' | %empty | '(' module_args optional_comma ')';
 
 module_args:
 	module_arg | module_args ',' module_arg;
 
 optional_comma:
-	',' | /* empty */;
+	',' | %empty;
 
 module_arg_opt_assignment:
 	'=' expr {
@@ -497,7 +497,7 @@ module_arg_opt_assignment:
 		} else
 			frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
 	} |
-	/* empty */;
+	%empty;
 
 module_arg:
 	TOK_ID {
@@ -565,15 +565,10 @@ package:
 	};
 
 package_body:
-	package_body package_body_stmt
-	| // optional
-	;
+	package_body package_body_stmt | %empty;
 
 package_body_stmt:
-	  typedef_decl
-	| localparam_decl
-	| param_decl
-	;
+	typedef_decl | localparam_decl | param_decl;
 
 interface:
 	TOK_INTERFACE {
@@ -599,7 +594,7 @@ interface:
 	};
 
 interface_body:
-	interface_body interface_body_stmt |;
+	interface_body interface_body_stmt | %empty;
 
 interface_body_stmt:
 	param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
@@ -613,7 +608,7 @@ non_opt_delay:
 	'#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
 
 delay:
-	non_opt_delay | /* empty */;
+	non_opt_delay | %empty;
 
 wire_type:
 	{
@@ -725,7 +720,7 @@ range:
 	non_opt_range {
 		$$ = $1;
 	} |
-	/* empty */ {
+	%empty {
 		$$ = NULL;
 	};
 
@@ -743,7 +738,7 @@ module_body:
 	/* the following line makes the generate..endgenrate keywords optional */
 	module_body gen_stmt |
 	module_body ';' |
-	/* empty */;
+	%empty;
 
 module_body_stmt:
 	task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
@@ -843,28 +838,28 @@ dpi_function_arg:
 
 opt_dpi_function_args:
 	'(' dpi_function_args ')' |
-	/* empty */;
+	%empty;
 
 dpi_function_args:
 	dpi_function_args ',' dpi_function_arg |
 	dpi_function_args ',' |
 	dpi_function_arg |
-	/* empty */;
+	%empty;
 
 opt_automatic:
 	TOK_AUTOMATIC |
-	/* empty */;
+	%empty;
 
 opt_signed:
 	TOK_SIGNED {
 		$$ = true;
 	} |
-	/* empty */ {
+	%empty {
 		$$ = false;
 	};
 
 task_func_args_opt:
-	'(' ')' | /* empty */ | '(' {
+	'(' ')' | %empty | '(' {
 		albuf = nullptr;
 		astbuf1 = nullptr;
 		astbuf2 = nullptr;
@@ -905,7 +900,7 @@ task_func_port:
 
 task_func_body:
 	task_func_body behavioral_stmt |
-	/* empty */;
+	%empty;
 
 /*************************** specify parser ***************************/
 
@@ -914,7 +909,7 @@ specify_block:
 
 specify_item_list:
 	specify_item specify_item_list |
-	/* empty */;
+	%empty;
 
 specify_item:
 	specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
@@ -1076,7 +1071,7 @@ specify_opt_triple:
 	',' specify_triple {
 		$$ = $2;
 	} |
-	/* empty */ {
+	%empty {
 		$$ = nullptr;
 	};
 
@@ -1084,7 +1079,7 @@ specify_if:
 	TOK_IF '(' expr ')' {
 		$$ = $3;
 	} |
-	/* empty */ {
+	%empty {
 		$$ = nullptr;
 	};
 
@@ -1092,7 +1087,7 @@ specify_condition:
 	TOK_SPECIFY_AND expr {
 		$$ = $2;
 	} |
-	/* empty */ {
+	%empty {
 		$$ = nullptr;
 	};
 
@@ -1125,7 +1120,7 @@ specify_target:
 specify_edge:
 	TOK_POSEDGE { $$ = 'p'; } |
 	TOK_NEGEDGE { $$ = 'n'; } |
-	{ $$ = 0; };
+	%empty { $$ = 0; };
 
 specify_rise_fall:
 	specify_triple {
@@ -1232,7 +1227,7 @@ specparam_assignment:
 	ignspec_id '=' ignspec_expr ;
 
 ignspec_opt_cond:
-	TOK_IF '(' ignspec_expr ')' | /* empty */;
+	TOK_IF '(' ignspec_expr ')' | %empty;
 
 path_declaration :
 	simple_path_declaration ';'
@@ -1283,9 +1278,7 @@ list_of_path_outputs :
 	list_of_path_outputs ',' specify_output_terminal_descriptor ;
 
 opt_polarity_operator :
-	'+'
-	| '-'
-	| ;
+	'+' | '-' | %empty;
 
 // Good enough for the time being
 specify_input_terminal_descriptor :
@@ -1334,7 +1327,7 @@ param_signed:
 		astbuf1->is_signed = true;
 	} | TOK_UNSIGNED {
 		astbuf1->is_signed = false;
-	} | /* empty */;
+	} | %empty;
 
 param_integer:
 	TOK_INTEGER {
@@ -1451,7 +1444,7 @@ enum_type: TOK_ENUM {
 
 enum_base_type: type_atom type_signing
 	| type_vec type_signing range	{ if ($3) astbuf1->children.push_back($3); }
-	| /* nothing */			{ astbuf1->is_reg = true; addRange(astbuf1); }
+	| %empty			{ astbuf1->is_reg = true; addRange(astbuf1); }
 	;
 
 type_atom: TOK_INTEGER		{ astbuf1->is_reg = true; addRange(astbuf1); }		// 4-state signed
@@ -1467,7 +1460,7 @@ type_vec: TOK_REG		{ astbuf1->is_reg   = true; }		// unsigned
 type_signing:
 	  TOK_SIGNED		{ astbuf1->is_signed = true; }
 	| TOK_UNSIGNED		{ astbuf1->is_signed = false; }
-	| // optional
+	| %empty
 	;
 
 enum_name_list: enum_name_decl
@@ -1491,7 +1484,7 @@ enum_name_decl:
 
 opt_enum_init:
 	'=' basic_expr		{ $$ = $2; }	// TODO: restrict this
-	| /* optional */	{ $$ = NULL; }
+	| %empty		{ $$ = NULL; }
 	;
 
 enum_var_list:
@@ -1532,14 +1525,14 @@ struct_union:
 struct_body: opt_packed '{' struct_member_list '}'
 	;
 
-opt_packed: TOK_PACKED opt_signed_struct
-	| { frontend_verilog_yyerror("Only PACKED supported at this time"); }
-	;
+opt_packed:
+	TOK_PACKED opt_signed_struct |
+	%empty { frontend_verilog_yyerror("Only PACKED supported at this time"); };
 
 opt_signed_struct:
 	  TOK_SIGNED		{ astbuf2->is_signed = true; }
 	| TOK_UNSIGNED		{ astbuf2->is_signed = false; }
-	| // default is unsigned
+	| %empty // default is unsigned
 	;
 
 struct_member_list: struct_member
@@ -1646,7 +1639,7 @@ wire_decl:
 	} opt_supply_wires ';';
 
 opt_supply_wires:
-	/* empty */ |
+	%empty |
 	opt_supply_wires ',' TOK_ID {
 		AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
 		AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
@@ -1877,13 +1870,13 @@ single_prim:
 	}
 
 cell_parameter_list_opt:
-	'#' '(' cell_parameter_list ')' | /* empty */;
+	'#' '(' cell_parameter_list ')' | %empty;
 
 cell_parameter_list:
 	cell_parameter | cell_parameter_list ',' cell_parameter;
 
 cell_parameter:
-	/* empty */ |
+	%empty |
 	expr {
 		AstNode *node = new AstNode(AST_PARASET);
 		astbuf1->children.push_back(node);
@@ -2041,7 +2034,7 @@ always_cond:
 	'@' ATTR_BEGIN ')' |
 	'@' '(' ATTR_END |
 	'@' '*' |
-	/* empty */;
+	%empty;
 
 always_events:
 	always_event |
@@ -2071,7 +2064,7 @@ opt_label:
 	':' TOK_ID {
 		$$ = $2;
 	} |
-	/* empty */ {
+	%empty {
 		$$ = NULL;
 	};
 
@@ -2079,7 +2072,7 @@ opt_sva_label:
 	TOK_SVA_LABEL ':' {
 		$$ = $1;
 	} |
-	/* empty */ {
+	%empty {
 		$$ = NULL;
 	};
 
@@ -2090,7 +2083,7 @@ opt_property:
 	TOK_FINAL {
 		$$ = false;
 	} |
-	/* empty */ {
+	%empty {
 		$$ = false;
 	};
 
@@ -2501,7 +2494,7 @@ behavioral_stmt:
 	};
 
 unique_case_attr:
-	/* empty */ {
+	%empty {
 		$$ = false;
 	} |
 	TOK_PRIORITY case_attr {
@@ -2537,11 +2530,11 @@ opt_synopsys_attr:
 		if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
 			ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
 	} |
-	/* empty */;
+	%empty;
 
 behavioral_stmt_list:
 	behavioral_stmt_list behavioral_stmt |
-	/* empty */;
+	%empty;
 
 optional_else:
 	TOK_ELSE {
@@ -2555,11 +2548,11 @@ optional_else:
 	} behavioral_stmt {
 		SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
 	} |
-	/* empty */ %prec FAKE_THEN;
+	%empty %prec FAKE_THEN;
 
 case_body:
 	case_body case_item |
-	/* empty */;
+	%empty;
 
 case_item:
 	{
@@ -2582,7 +2575,7 @@ case_item:
 
 gen_case_body:
 	gen_case_body gen_case_item |
-	/* empty */;
+	%empty;
 
 gen_case_item:
 	{
@@ -2666,11 +2659,11 @@ lvalue_concat_list:
 
 opt_arg_list:
 	'(' arg_list optional_comma ')' |
-	/* empty */;
+	%empty;
 
 arg_list:
 	arg_list2 |
-	/* empty */;
+	%empty;
 
 arg_list2:
 	single_arg |
@@ -2683,7 +2676,7 @@ single_arg:
 
 module_gen_body:
 	module_gen_body gen_stmt_or_module_body_stmt |
-	/* empty */;
+	%empty;
 
 gen_stmt_or_module_body_stmt:
 	gen_stmt | module_body_stmt |
@@ -2762,7 +2755,7 @@ gen_stmt_block:
 	};
 
 opt_gen_else:
-	TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
+	TOK_ELSE gen_stmt_block | %empty %prec FAKE_THEN;
 
 expr:
 	basic_expr {