From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 15 Sep 2023 21:47:00 +0000 (-0700)
Subject: fix scalar EXTRA2 in EXTRA2/3 decoding algorithms
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24576f370d5b0b0282b821062c66e1ff39ab8019;p=libreriscv.git

fix scalar EXTRA2 in EXTRA2/3 decoding algorithms
---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index c623c123a..8bc7f784b 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -1194,13 +1194,15 @@ A pseudocode algorithm explains the relationship, for INT/FP (see
 
 ```
     if extra3_mode:
-        spec = EXTRA3
-    else:
-        spec = EXTRA2 << 1 # same as EXTRA3, shifted
-    if spec[0]: # vector
-         return (RA << 2) | spec[1:2]
-    else:         # scalar
-         return (spec[1:2] << 5) | RA
+        if EXTRA3[0]: # vector
+            return (RA << 2) | EXTRA3[1:2]
+        else:         # scalar
+            return (EXTRA3[1:2] << 5) | RA
+    else:  # EXTRA2 mode
+        if EXTRA2[0]: # vector
+            return (RA << 2) | (EXTRA2[1] << 1)
+        else:
+            return (EXTRA2[1] << 5) | RA
 ```
 
 Future versions may extend to 256 by shifting Vector numbering up.
diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 73426d430..60c8962c7 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -615,17 +615,22 @@ applies, **not** the `CR_bit` portion (bits 3-4):
 
 ```
     if extra3_mode:
-        spec = EXTRA3
+        is_vec = EXTRA3[0]
+        extra = EXTRA3[1:2]
     else:
-        spec = EXTRA2<<1 | 0b0
-    if spec[0]:
-       # vector constructs "BA[0:2] spec[1:2] 00 BA[3:4]"
-       return ((BA >> 2)<<6) | # hi 3 bits shifted up
-              (spec[1:2]<<4) | # to make room for these
-              (BA & 0b11)      # CR_bit on the end
+        is_vec = EXTRA2[0]
+        if is_vec:
+            extra = EXTRA2[1] << 1
+        else:
+            extra = EXTRA2[1]
+    if is_vec:
+        # vector constructs "BA[0:2] extra 00 BA[3:4]"
+        return ((BA >> 2) << 6) | # hi 3 bits shifted up
+               (extra << 4) |     # to make room for these
+               (BA & 0b11)        # CR_bit on the end
     else:
-       # scalar constructs "00 spec[1:2] BA[0:4]"
-       return (spec[1:2] << 5) | BA
+        # scalar constructs "00 extra BA[0:4]"
+        return (extra << 5) | BA
 ```
 
 Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
@@ -633,12 +638,12 @@ algorithm to determine CR\_reg is modified to as follows:
 
 ```
     CR_index = (BA>>2)      # top 3 bits 
-    if spec[0]:
+    if is_vec:
         # vector mode, 0-124 increments of 4
-        CR_index = (CR_index<<4) | (spec[1:2] << 2)
+        CR_index = (CR_index << 4) | (extra << 2)
     else:
         # scalar mode, 0-32 increments of 1
-        CR_index = (spec[1:2]<<3) | CR_index
+        CR_index = (extra << 3) | CR_index
     # same as for v3.0/v3.1 from this point onwards
     bit_index = (BA & 0b11) # low 2 bits
     CR_reg = CR{CR_index}     # get the CR