From: bugzilla-daemon Date: Fri, 3 Apr 2020 12:05:29 +0000 (+0000) Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=246394b89627570ad77e07b91518329ec6c7b187;p=libre-riscv-dev.git [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen --- diff --git a/00/8e25b951b75bcb1689c574475b4d9ed99e3a1a b/00/8e25b951b75bcb1689c574475b4d9ed99e3a1a new file mode 100644 index 0000000..8830163 --- /dev/null +++ b/00/8e25b951b75bcb1689c574475b4d9ed99e3a1a @@ -0,0 +1,186 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Fri, 03 Apr 2020 13:05:31 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jKL4k-00088p-Jo; Fri, 03 Apr 2020 13:05:30 +0100 +Received: from localhost ([127.0.0.1] helo=bugs.libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) id 1jKL4j-00088h-5T + for libre-riscv-dev@lists.libre-riscv.org; Fri, 03 Apr 2020 13:05:29 +0100 +From: bugzilla-daemon@libre-riscv.org +To: libre-riscv-dev@lists.libre-riscv.org +Date: Fri, 03 Apr 2020 12:05:29 +0000 +X-Bugzilla-Reason: CC +X-Bugzilla-Type: changed +X-Bugzilla-Watch-Reason: None +X-Bugzilla-Product: Libre-SOC's first SoC +X-Bugzilla-Component: Source Code +X-Bugzilla-Version: unspecified +X-Bugzilla-Keywords: +X-Bugzilla-Severity: enhancement +X-Bugzilla-Who: lkcl@lkcl.net +X-Bugzilla-Status: CONFIRMED +X-Bugzilla-Resolution: +X-Bugzilla-Priority: --- +X-Bugzilla-Assigned-To: lkcl@lkcl.net +X-Bugzilla-Flags: +X-Bugzilla-Changed-Fields: +Message-ID: +In-Reply-To: +References: +X-Bugzilla-URL: http://bugs.libre-riscv.org/ +Auto-Submitted: auto-generated +MIME-Version: 1.0 +Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + 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