From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 May 2021 16:38:52 +0000 (+0100)
Subject: add fast3 to PowerDecoder and regspec map
X-Git-Tag: 0.0.3~90
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2466e66f8b4445fc77a94b86105c102805e3cc26;p=openpower-isa.git

add fast3 to PowerDecoder and regspec map
needed for SVSRR0
---

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index 0bb7c641..12f58433 100644
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -111,10 +111,13 @@ class Decode2ToExecute1Type(RecordObject):
         self.xer_in = Signal(3, reset_less=True)   # xer might be read
         self.xer_out = Signal(reset_less=True)  # xer might be written
 
+        # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
         self.read_fast1 = Data(3, name="fast1")
         self.read_fast2 = Data(3, name="fast2")
+        self.read_fast3 = Data(3, name="fast3")   # really only for SVSRR0
         self.write_fast1 = Data(3, name="fasto1")
         self.write_fast2 = Data(3, name="fasto2")
+        self.write_fast3 = Data(3, name="fasto3") # likewise
 
         self.read_cr1 = Data(7, name="cr_in1")
         self.read_cr2 = Data(7, name="cr_in2")
diff --git a/src/openpower/decoder/power_regspec_map.py b/src/openpower/decoder/power_regspec_map.py
index d97dbb4e..eee04967 100644
--- a/src/openpower/decoder/power_regspec_map.py
+++ b/src/openpower/decoder/power_regspec_map.py
@@ -105,6 +105,8 @@ def regspec_decode_read(e, regfile, name):
             return e.read_fast1.ok, e.read_fast1.data
         if name == 'fast2':
             return e.read_fast2.ok, e.read_fast2.data
+        if name == 'fast3':
+            return e.read_fast3.ok, e.read_fast3.data
 
     # SPR regfile
 
@@ -172,6 +174,8 @@ def regspec_decode_write(e, regfile, name):
             return e.write_fast1, e.write_fast1.data
         if name == 'fast2':
             return e.write_fast2, e.write_fast2.data
+        if name == 'fast3':
+            return e.write_fast3, e.write_fast3.data
 
     # SPR regfile
 
diff --git a/src/openpower/test/common.py b/src/openpower/test/common.py
index c62a803b..33a873db 100644
--- a/src/openpower/test/common.py
+++ b/src/openpower/test/common.py
@@ -181,6 +181,14 @@ class ALUHelpers:
             spr2_data = sim.spr[spr2_sel].value
             res['fast2'] = spr2_data
 
+    def get_sim_fast_spr3(res, sim, dec2):
+        fast3_en = yield dec2.e.read_fast3.ok
+        if fast3_en:
+            fast3_sel = yield dec2.e.read_fast3.data
+            spr3_sel = fast_reg_to_spr(fast3_sel)
+            spr3_data = sim.spr[spr3_sel].value
+            res['fast3'] = spr3_data
+
     def get_sim_cr_a(res, sim, dec2):
         cridx_ok = yield dec2.e.read_cr1.ok
         if cridx_ok:
@@ -293,6 +301,10 @@ class ALUHelpers:
         if 'fast2' in inp:
             yield alu.p.data_i.fast2.eq(inp['fast2'])
 
+    def set_fast_spr3(alu, dec2, inp):
+        if 'fast3' in inp:
+            yield alu.p.data_i.fast3.eq(inp['fast3'])
+
     def set_cr_a(alu, dec2, inp):
         if 'cr_a' in inp:
             yield alu.p.data_i.cr_a.eq(inp['cr_a'])