From: lkcl <lkcl@web>
Date: Thu, 24 Dec 2020 21:06:03 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~943
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=24732bde6bc6e1c67f13eb64231f8f6190709846;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index b963a065d..37846cba9 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -188,14 +188,11 @@ The above functionality pretty much covers around 85% of Vector ISA needs.  Pred
 Experienced Vector ISA readers will however have noted that VCOMPRESS and VEXPAND are missing, as is Vector "reduce" (mapreduce) capability.  Compress and Expand are covered by Twin Predication, and yet to also be covered is fail-on-first, CR-based result predication, and Subvectors and Swizzle.
 
 
-## SUBVL Pseudocode <a name="subvl-pseudocode"></a>
+## SUBVL <a name="subvl"></a>
 
 Adding in support for SUBVL is a matter of adding in an extra inner
 for-loop, where register src and dest are still incremented inside the
-inner part. Note that the predication is still taken from the VL index.
-
-So whilst elements are indexed by "(i * SUBVL + s)", predicate bits are
-indexed by "(i)"
+inner part.  Predication is still taken from the VL index, however it is applied to the whole subvector:
 
     function op_add(rd, rs1, rs2) # add not VADD!
       int id=0, irs1=0, irs2=0;